Routing methods for use in a logic emulation system

• US 5,657,241 A
• Filed: 06/06/1995
• Issued: 08/12/1997
• Est. Priority Date: 10/05/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Butts, Michael R., Batcheller, Jon A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/471,678
• Time in Patent Office: 798 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500
• US Class Current: 716/103
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims

1. A method for routing a design into a hardware logic emulation system, the design comprising a user-provided netlist description, the user-provided netlist description comprising a first set of primitives, the hardware logic emulation system comprising a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, at least some other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in another of said selected electrically reconfigurable devices containing functional logic elements, the method comprising the steps of:

converting the user-provided netlist description into an emulation netlist, said emulation netlist being functionally equivalent the user-provided netlist but having primitives compatible with the functional logic elements of said electrically reconfigurable devices;

partitioning said emulation netlist into a plurality of partitions, each of said plurality partitions comprising a subset of the primitives of said emulation netlist;

issuing first statements for each primitive within each partition of said plurality of partitions of said emulation netlist, said first statements defining where said primitive is to be placed within said electrically reconfigurable devices containing reprogrammable functional logic elements;

listing cut nets, each of said cut nets comprising a net which will have to pass from a first of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements, through a first of said electrically reconfigurable devices containing reprogrammable electrical conductors, to a second of said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements;

selecting said electrically reconfigurable devices containing reprogrammable electrical conductors which can best interconnect said cut nets; and

issuing statements for each of said cut nets which define where each of said cut nets is placed in the selected electrically reconfigurable devices containing reprogrammable electrical conductors.