Vision coprocessing
First Claim
1. A digital image processing system includingA. bus means for carrying control, data and address signals,B. memory means, coupled to said bus means, for storing digital image data and for responding to access control signals on said bus means for transferring digital image data therewith,C. CPU means, coupled to said bus means, for applying said access control signals thereto for controlling the transfer of digital image data therewith, said CPU means including address means for applying address signals to the bus means, in connection with said access control signals, to locate data being transferred therewith,D. video input means, coupled to said memory means, for acquiring digital image data and for storing said digital image data in said memory means, andE. image data co-processing means, coupled to said bus means, for responding to said control and address signals on said bus means for processing digital image data received therefrom,F. said address means including means for applying an address signal from a first selected set of address signals to the bus means in connection with an access control signal,said memory means including means for responding to that address signal for transferring data in accord with that access control signal,said image data co-processing means including means for responding to that address signal for ignoring data transfer with said bus means, andG. said address means includes means for applying an address signal from a second selected set of address signals to the bus means in connection with an access control signal,said image data co-processing means including means for responding to that address signal for transferring digital image data to said bus means,said memory means including means for responding to that address signal for transferring data from said bus means for storage therein.
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Abstract
A coprocessor in an image processing system is coupled to the bus to which a CPU and RAM holding image data are also coupled. The coprocessor extracts an input pixel stream corresponding to input images from selected bus transactions, performs computations on the input stream to produce output pixel streams corresponding to output images, and inserts the output pixel streams into selected CPU-to-memory bus transactions so that the memory stores the data. The CPU generates the selected bus transactions with specially marked address and/or control signals. The coprocessor includes a lookup table, and a first row delay. The row delay accumulates the three most recent rows of input pixels, which are sent to Sobel and rank processing sections for neighborhood processing. The results are thresholded and formatted, and are either output directly or passed through an additional pair of row delays to accumulate three rows of result data for neighborhood peak detection.
53 Citations
36 Claims
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1. A digital image processing system including
A. bus means for carrying control, data and address signals, B. memory means, coupled to said bus means, for storing digital image data and for responding to access control signals on said bus means for transferring digital image data therewith, C. CPU means, coupled to said bus means, for applying said access control signals thereto for controlling the transfer of digital image data therewith, said CPU means including address means for applying address signals to the bus means, in connection with said access control signals, to locate data being transferred therewith, D. video input means, coupled to said memory means, for acquiring digital image data and for storing said digital image data in said memory means, and E. image data co-processing means, coupled to said bus means, for responding to said control and address signals on said bus means for processing digital image data received therefrom, F. said address means including means for applying an address signal from a first selected set of address signals to the bus means in connection with an access control signal, said memory means including means for responding to that address signal for transferring data in accord with that access control signal, said image data co-processing means including means for responding to that address signal for ignoring data transfer with said bus means, and G. said address means includes means for applying an address signal from a second selected set of address signals to the bus means in connection with an access control signal, said image data co-processing means including means for responding to that address signal for transferring digital image data to said bus means, said memory means including means for responding to that address signal for transferring data from said bus means for storage therein.
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6. A digital image processing system comprising
A. image source means generating digital image data representative of one or more images, B. image data co-processing means, coupled to said image source means, for processing digital image data received therefrom, and C. CPU means, coupled to said image source means and to said image data co-processing means, for generating and applying thereto signals to i) control the transfer of rows of digital image data from said image source means to said image data co-processing means, each said row comprising adjacent portions of an image along a first axis thereof, said transferred rows being any of (a) successive rows of a single image adjacent along a second axis, and (b) single corresponding rows of successive images, and ii) control the processing of said transferred rows by said image data co-processing means, D. said image data co-processing means comprising i) input means for inputting said rows of said digital image data, ii) row delay means, coupled to said input means, for accumulating said rows digital image data, said accumulated rows being any of (a) said successive rows of a single image adjacent along a second axis, and (b) said single corresponding rows of successive images, iii) neighborhood processing means, coupled to said row delay means, for responding to control signals received from said CPU means to selectively process successive rows of a single image received therefrom, and iv) row processing means, coupled to said row delay means, for responding to control signals received from said CPU means to selectively process said single corresponding rows of successive images.
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7. A digital image processing system comprising
A. bus means for carrying control and data and address signals, B. image source means, coupled with said bus means, for generating digital image data representative of one or more images and for transferring that data with said bus means, C. image data co-processing means, coupled to said bus means, for processing digital image data received therefrom, D. CPU means, coupled to said bus means, for generating and applying thereto signals to i) control the transfer of rows of digital image data from said image source means to said bus means, each said row comprising adjacent portions of an image along a first axis thereof, said transferred rows being any of (a) successive rows of a single image adjacent along a second axis; - and (b) single corresponding rows of successive images,
ii) control the processing of said transferred rows by said image data co-processing means, E. said image data co-processing means comprising i) input means, coupled to said bus means, for inputting said rows of said digital image data, ii) row delay means, coupled to said input means, for accumulating said rows of digital image data, said accumulated rows being any of (a) said successive rows of a single image adjacent along a second axis, and (b) said single corresponding rows of successive images, iii) neighborhood processing means, coupled to said row delay means, for responding to said control signals to selectively process successive rows of a single image received therefrom, iv) row processing means, coupled to said row delay means, for responding to control signals received from said CPU means to selectively process said single rows of corresponding successive images, and v) means, coupled to said neighborhood processing means and said row processing means, for selectively transferring processed image data to said bus means.
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9. A digital image processing apparatus comprising:
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A. a programmable computational element; B. a random access memory; C. a bus for carrying address, data, and control signals, that connects said computational element to said memory for the purpose of transferring data between them under control of said computational element; D. input circuits capable of acquiring one or more digital input images and storing said input images in said memory; E. a pixel processor operatively connected to said bus, having; i) extracting means for extracting an input pixel stream, corresponding to one or more input images, from selected bus transactions that are specially marked by at least one of selected address and control signals reserved for that purpose; ii) performing means for performing some computation on said input pixel stream to produce one or more first output pixel streams, corresponding to one or more output images, wherein each output value is some function of one or more input values; and iii) inserting means for inserting said one or more first output pixel streams into selected computational element-to-memory bus transactions that are specially marked by at least one of selected address and control signals reserved for that purpose, and in such a way that the memory stores the data supplied by the pixel processor, and F. said computational element having means to generate the said selected bus transactions with the said specially marked address and control signals. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29)
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30. A method for processing digital image data in a system of the type having
a bus for carrying control, data and address signals, a memory coupled to said bus, for storing digital image data and for responding to access control signals on said bus for transferring digital image data therewith, a video input, coupled to said bus, for acquiring digital image data and for responding to access control signals on said bus for transferring digital image data thereto, an image data coprocessor, coupled to said bus, for responding to access control signals on said bus for processing digital image data received therefrom for enhancement thereof, a CPU, coupled to said bus, for applying said access control signals to the bus for controlling said transfer of digital image data with said bus, said CPU including an address element for applying address signals to the bus, in connection with said access control signals, to locate data being transferred in connection therewith, the method comprising: -
A. signalling, when certain preselected image data from said memory is on said bus, that the data be written to the coprocessor, B. providing for processing of the image data by the coprocessor, and C. at a preselected time later, signalling that image data output from said coprocessor be written to the memory means. - View Dependent Claims (31, 32, 33, 34)
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35. A method for digital image processing in a system comprising
image source means generating digital image data representative of one or more images, image data co-processing means, coupled to said image source means, for processing digital image data received therefrom, CPU means, coupled to said image source means to said image data co-processing means, for generating and applying thereto control signals to i) control the transfer of rows of digital image data from said image source means to said image data co-processing means, each said row comprising adjacent portions of an image along a first axis thereof, said transferred rows being any of (a) successive rows of a single image adjacent along a second axis, and (b) single corresponding rows of successive images, ii) control the processing of said transferred rows by said image data co-processing means, the method comprising A. inputting said rows of said digital image data, B. accumulating said rows of digital image data, said accumulated rows being any of (a) said successive rows of a single image adjacent along a second axis, and (b) said single corresponding rows of successive images, C. selectively responding to said control signals to selectively process successive rows of a single image received therefrom, D. selectively responding to control signals received from said CPU means to selectively process said single corresponding rows of successive images.
Specification