Audio decoder circuit and method of operation

• US 5,657,454 A
• Filed: 06/07/1995
• Issued: 08/12/1997
• Est. Priority Date: 02/22/1992
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Li, Stephen H., Laczko, Frank L. Sr., Walker, Karen L., Benbassat, Gerard, Kam, Shiu Wai
• Primary Examiner(s): Harrell, Robert B.
• Assistant Examiner(s): Najjar, Saleh
• Application Number:
  US08/477,028
• Time in Patent Office: 797 Days
• Field of Search: 341/144, 370/94.1, 370/13, 375/8, 375/242, 375/220, 375/240, 381/36, 381/2, 348/607.14, 348/405, 348/441, 371/37.7, 371/53, 360/19.1, 360/27, 395/250, 395/563, 395/375, 395/2.38
• US Class Current: 375/242
• CPC Class Codes: H04B 1/665 using psychoacoustic properties of the ear, e.g. masking effect
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/44 Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/70 characterised by syntax aspects related to video coding, e.g. related to compression standards
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
• CPC Class Codes: H04N 21/42607 for processing the incoming bitstream
• CPC Class Codes: H04N 21/4305 Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083
• CPC Class Codes: H04N 21/43072 of multiple content streams on the same device
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/4398 involving reformatting operations of audio signals details of audio signal transcoding G10L19/173
• CPC Class Codes: H04N 5/04 Synchronising for television systems using pulse code modulation H04N7/56
• CPC Class Codes: H04N 5/602 for digital sound signals
• CPC Class Codes: H04S 1/007 in which the audio signals are in digital form data reduction aspects thereof based on psychoacoustics G10L19/02

Abstract

A data processing system (10) is disclosed which comprises a microprocessor host (12) coupled to a decoding system (14). A host interface block (18) receives a bit stream and passes bit stream on to a system decoder block (20). The system decoder block (20) extracts the appropriate data from the bit stream and loads an input buffer (24) or an optional external buffer (26). An audio decoder block (28) retrieves the data from the input buffer (24) and generates scale factor indices, bit per code word values and subband samples which are stored in an arithmetic unit buffer (30). A hardware filter arithmetic unit block (32) retrieves the information from the arithmetic unit buffer (30) and dequantizes, transforms and filters the data to generate PCM output data which is loaded into a PCM buffer (34). The data within the PCM buffer (34) is output by a PCM output block (36) to a digital-to-analog converter (16).

Claims

1. A data processing system for processing an encoded bit stream retrieved from storage in a first buffer circuit and for outputting processed data to a second buffer circuit, comprising:

an arithmetic logic unit operable to perform arithmetic and logical operations;

an execution control state machine coupled to said arithmetic logic unit and operable to direct the performance of said arithmetic and logical operations;

an instruction memory for storing sequences of microcode instructions executable by the system to process the encoded bit stream;

multiplexer circuitry with a first input connected to said execution control state machine, a second input connected to said instruction memory and an output connected to said arithmetic logic unit and operable to allow said arithmetic logic unit to be responsive to an instruction having a predetermined format from either said execution control state machine or said instruction memory; and

said instruction memory storing a set of said microcode instructions operable to be executed by the system including said arithmetic logic unit and said execution control state machine to retrieve frames of data from the first buffer circuit and to decode the retrieved data and output scale factor information and coded sample information to the second buffer circuit.

2. The data processing system of claim 1 and further comprising a format register for storing information indicating the format of the frame of data being processed by the system, said instruction memory storing processing routines associated with the processing of different formats of encoded data, the system responsive to said data identifying the format to select and execute the appropriate routines stored in said instruction memory associated with the indicated format.

3. The data processing system of claim 2 wherein said frames of data comprises audio data encoded using a predetermined standard syntax at a predetermined bit rate, said format register operable to store data identifying the bit rate used to encode the frame of audio data being processed by the system.

4. The data processing system of claim 2 wherein said frames of data comprise audio data encoded using a particular layer associated with said standard syntax, said format register operable to store data identifying the particular layer used to encode the frame of audio data being processed by the system, said instruction memory storing processing routines associated with the processing of different layers of encoded data, the system responsive to said data identifying the particular layer to select and execute the appropriate routines stored in said instruction memory associated with the indicated layer.

5. The data processing system of claim 1 wherein said frames of data comprise encoded audio data and wherein said instruction memory is operable to store error concealment routines selectable and executable by the system to output data other than the frame currently being processed when it is determined by the system that said current frame contains error.

6. The data processing system of claim 5 wherein the system is operable to determine the size of the first buffer in order to determine whether a valid frame of data can be stored in the first buffer for use in said error concealment routines, the system responsive to the size of the first buffer to select and execute particular error concealment routines requiring the storage of a valid frame of data in addition to the storage of the frame being processed by system if said storage of a valid frame of data is possible with the determined size of the first buffer.

7. The data processing system of claim 6 wherein one of said error concealment routines causes the system to output the last processed valid frame of data in place of the frame currently being processed by the system when the frame currently being processed is found to contain errors by the system.

8. The data processing system of claim 5 wherein one of said error concealment routines causes the system to output data corresponding to muted audio output.

9. The data processing system of claim 5 wherein one of said error concealment routines causes the system to discard a frame of audio data and begin processing a new frame of audio data.

10. The data processing system of claim 1 wherein said frames of data comprise encoded audio data divisible into subbands and wherein said instruction memory is operable to store processing routines selectable and executable by the system to access predetermined factors associated with each of the subbands and to associate said predetermined factors with said frames of audio data and to output processed data to the second buffer such that the subbands are scaled by the predetermined factors such that volumes associated with each of the subbands may be independently adjusted using said predetermined factors.

11. The data processing system of claim 1 wherein said frames of data comprise encoded audio data divisible into stereo channels and wherein said instruction memory is operable to store processing routines selectable and executable by the system to access predetermined factors associated with each of the stereo channels and to associate said predetermined factors with said frames of audio data and to output data to the second buffer such that said stereo channels are scaled by the predetermined factors such that volumes associated with each of said stereo channels may be independently adjusted using said predetermined factors.

12. The data processing system of claim 1 wherein at least one of said microcode instructions comprises an instruction operable to cause the system to retrieve a predetermined number of bits of data from the first buffer.

13. The data processing system of claim 1 wherein at least one of said microcode instructions comprises an instruction operable to cause the system to retrieve a predetermined number of bits of data from the first buffer and to calculate a cyclic redundancy code value associated with the retrieved bits.

14. The data processing system of claim 1 wherein at least one of said microcode instructions comprises a synchronization instruction operable to cause the system to retrieve a bits of data from the first buffer and to search the retrieved bits for a predetermined bit pattern such that the system can acquire synchronization in the bit sequence stored in the first buffer by executing said synchronization instruction.

15. The data processing system of claim 1 and further comprising an ancillary data register, at least one of said microcode instructions comprising an ancillary data instruction operable to cause the system to retrieve a predetermined number of ancillary data bits of data from the first buffer and to store said ancillary data bits in said ancillary data register.

16. The data processing system of claim 15 wherein the system is operable to selectably output information indicating the presence of ancillary data in said ancillary data register.

17. The data processing system of claim 15 wherein the system is operable to selectably halt processing of audio data prior to overwriting ancillary data stored in said ancillary data register with new ancillary data.

18. The data processing system of claim 1, further comprising:

data shifter circuitry with a load counter to maintain a bit count and a shift counter to maintain a shift count and having an input connected to said first buffer and an output connected to said arithmetic logic unit and operable to be loaded with a first predetermined number of bits from said encoded bit stream and to shift a specified number of bits of said first predetermined number of bits of encoded bit stream into said arithmetic logic unit, and further operable to automatically load a second predetermined number of bits from said encoded bit stream if said shift count is greater than said bit count.

19. A method for processing by a data processing system an encoded audio bit stream retrieved from storage in a first buffer circuit and for outputting processed data to a second buffer circuit, comprising:

providing an arithmetic logic unit operable to perform arithmetic and logical operations;

providing an execution control state machine coupled to said arithmetic logic unit and operable to direct the performance of said arithmetic and logical operations;

providing an instruction memory for storing sequences of microcode instructions executable by the system to process the encoded bit stream;

processing said encoded audio bit stream by executing a set of said microcode instructions stored in said instruction memory by the system including said arithmetic logic unit and said execution control state machine to retrieve frames of data from the first buffer circuit and to decode the retrieved data and output scale factor information and coded sample information to the second buffer circuit;

storing error concealment routines in said instruction memory selectable and executable by the system to output data other than the frame currently being processed when it is determined by the system that said current frame contains error,

determining the size of the first buffer in order to determine whether a valid frame of audio data can be stored in the first buffer for use in said error concealment routines,

selecting and executing particular error concealment routines requiring the storage of a valid frame of data in addition to the storage of the frame being processed by the system if said storage of a valid frame of data is possible with the determined size of the first buffer.

20. The method of claim 19 further comprising comparing said determined size of the first buffer to the size of each frame before processing audio data for each frame in order to provide adaptable error concealment for variable frame lengths.

21. The method of claim 19 wherein one of said error concealment routines comprises outputting the last processed valid frame of data in place of the frame currently being processed by the system when the frame currently being processed is found to contain errors by the system.

22. The method of claim 21, further comprising:

muting the output of said processed data if said determining step determined that said buffer could not be used to store said valid frame of audio data or if said step of outputting the last valid frame has been repeated more than a predetermined number of times.

23. The method of claim 19, wherein the step of processing further comprises:

locating a first predetermined sync word within a first frame of said encoded audio bit stream in order to correctly decode said encoded bit stream;

storing said first frame of said encoded audio bit stream in said first buffer;

confirming the location of a second predetermined sync word in said second frame of said encoded audio bit stream with respect to said first predetermined sync word before decoding said first frame of encoded audio data;

repeating said steps of locating said first predetermined sync word and confirming the location of said second predetermined sync word by shifting said encoded audio bit stream by one bit if said second predetermined sync word is not found at an expected location in said second frame of said encoded audio bit stream; and

selecting and executing a first particular error routine if said second predetermined sync word is not found at said expected location in said second frame of said encoded audio bit stream.

24. The method of claim 23, wherein the step of processing further comprises:

performing a cyclic redundancy check (CRC) of said first frame of said encoded audio bit stream; and

selecting and executing a second particular error routine if said CRC step indicates an error in said first frame of said encoded audio bit stream.

25. The method of claim 24, wherein said first error routine and said second error routine form processed data for outputting in a different way.

26. The method of claim 19, wherein the step of processing further comprises:

locating a first predetermined sync word within a first frame of said encoded audio bit stream in order to correctly decode said encoded bit streams;

storing said first frame of said encoded audio bit stream in said first buffer;

decoding a header field in said first frame of said encoded audio data; and

repeating said locating step by shifting said encoded audio bit stream by one bit if said decoding step produced a syntax error in said header field.