Status indicator for a host adapter

• US 5,657,455 A
• Filed: 09/07/1994
• Issued: 08/12/1997
• Est. Priority Date: 09/07/1994
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F., Fannin, Charles S.
• Primary Examiner(s): Auve, Glenn A.
• Assistant Examiner(s): Travis, John
• Application Number:
  US08/301,458
• Time in Patent Office: 1,070 Days
• Field of Search: 395/280, 395/284, 395/307, 395/309, 395/312
• US Class Current: 710/100
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

A host adapter for transferring data between a system bus and an input/output (I/O) bus is implemented as an integrated circuit having a data transfer circuit and a status indicator circuit. The status indicator circuit selectively supplies one of a number of status signals from the data transfer circuit as a signal on a status indicator terminal of the host adapter. Therefore, a light emitting diode connected to the status indicator terminal indicates in real time the status of data transfer, such as usage of the system bus, or I/O bus, or execution time of one or more instructions by the host adapter.

Claims

1. A host adapter integrated circuit comprising:

a plurality of first terminals for connection to a first bus;

a plurality of second terminals for connection to a second bus;

a data transfer circuit for transferring data between said first bus and said second bus, said data transfer circuit comprising;

a plurality of first lines connected to said plurality of first terminals;

a plurality of second lines connected to said plurality of second terminals;

a plurality of third lines; and

a plurality of fourth lines;

a status indicator terminal for indicating status of at least a portion of said data transfer circuitry; and

a status switching circuit comprising;

an output line coupled to said status indicator terminal;

a plurality of function input lines, each function input line being coupled to a data transfer circuit third line; and

a plurality of function enable lines, each function enable line being coupled to a data transfer circuit fourth line;

wherein said status switching circuit couples said output line to a function input line selected from said plurality of function input lines using an active signal on one of said function enable lines and

further wherein said status switching circuit decouples said output line from said selected function input line in response to an inactive signal on said one functional enable line.

2. The host adapter integrated circuit of claim 1 wherein said status switching circuit has a default function input line connected to said data transfer circuit;

and

further wherein said status switching circuit couples said output line to said default function input line in response to an inactive signal on said function enable line.

3. The host adapter integrated circuit of claim 2 wherein said data transfer circuit further comprises a first bus module for communication with said first bus, said first bus module being connected to said default function input line;

and

further wherein said first bus module drives a signal on said default function input line active while said first bus module communicates with said first bus and otherwise drives said signal inactive.

4. The host adapter integrated circuit of claim 1 further comprising a status storage element having an enable storage unit;

wherein said host adapter integrated circuit drives a signal on said function enable line depending on the value of said enable storage unit in said status storage element.

5. The host adapter integrated circuit of claim 4 wherein said enable storage unit is a flip-flop.

6. The host adapter integrated circuit of claim 1 further comprising a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said function input line depending on the value of said input storage unit in said status storage element.

7. A host adapter integrated circuit comprising:

a plurality of first terminals;

a plurality of second terminals;

a data transfer circuit comprising;

a plurality of first lines connected to said plurality of first terminals;

a plurality of second lines connected to said plurality of second terminals;

a third line; and

a fourth line;

an external status indicator terminal; and

a status switching circuit comprising;

an output line coupled to said external status indicator terminal;

a function input line connected to said data transfer circuit third line; and

a function enable line connected to said data transfer circuit fourth line;

wherein said status switching circuit couples said output line to said function input line in response to an active signal on said function enable line and decouples said output line from said function input line in response to an inactive signal on said functional enable line;

wherein said status switching circuit has a function disable line; and

further wherein said status switching circuit disconnects said output line from every one of said plurality of function input lines in response to an active signal on said function disable line.

8. A host adapter integrated circuit comprising:

a plurality of first terminals;

a plurality of second terminals;

a data transfer circuit comprising;

a plurality of first lines connected to said plurality of first terminals;

a plurality of second lines connected to said plurality of second terminals;

a third line; and

a fourth line;

an external status indicator terminal; and

a status switching circuit comprising;

an output line coupled to said status indicator terminal;

a function input line connected to said data transfer circuit third line; and

a function enable line connected to said data transfer circuit fourth line;

wherein said status switching circuit couples said output line to said function input line in response to an active signal on said function enable line and decouples said output line from said function input line in response to an inactive signal on said functional enable line;

further comprising a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said function input line depending on the value of said input storage unit in said status storage element;

wherein said status switching circuit has a function disable line; and

further wherein said status switching circuit sets said input storage unit in said status storage element and disconnects said output line from said function input line, in response to an active signal on said function disable line, and

further wherein said status switching circuit connects said output line to said function input line, in response to an inactive signal on said function disable line subsequent to said active signal.

9. A host adapter integrated circuit comprising:

a plurality of first terminals capable of connection to a first bus;

a plurality of second terminals capable of connection to a second bus;

a data transfer circuit comprising;

a plurality of first lines connected to said plurality of first terminals;

a plurality of second lines connected to said plurality of second terminals;

a third line; and

a fourth line;

an external status indicator terminal;

a status switching circuit comprising;

an output line coupled to said external status indicator terminal;

a function input line connected to said data transfer circuit third line; and

a function enable line connected to said data transfer circuit fourth line; and

a status storage element having an enable storage unit;

wherein said status switching circuit couples said output line to said function input line in response to an active signal on said function enable line and decouples said output line from said function input line in response to an inactive signal on said functional enable line;

wherein said host adapter integrated circuit drives a signal on said function enable line depending on the value of said enable storage unit in said status storage element;

wherein said first bus is a I/O bus connected to a peripheral device, said second bus is a system bus connected to a memory and said status storage element is in the address space of said second bus.

10. A device comprising:

a bus module having a line;

a status switching circuit having;

an output line;

a default function input line coupled to said line of said bus module;

a first function input line;

a first function enable line; and

wherein said status switching circuit selectively couples and decouples said output line to one of said first function input line and said default function input line in response to a signal on said first function enable line; and

further wherein said status switching circuit is included on an integrated circuit having a plurality of bus terminals and an external terminal different from said bus terminals, and said output line of said status switching circuit is coupled to said external terminal.

11. The device of claim 10 further comprising a status storage element having an input storage unit and an enable storage unit, wherein said first function input line carries a signal derived from the value of said input storage unit and said first function enable line carries a signal derived from the value of said enable storage unit.

12. The device of claim 10 wherein said status switching circuit further comprises a second function input line and a second function enable line,

further wherein said status switching circuit disconnects said output line from said default function input line and from said first function input line irrespective of said signal on said first function enable line and connects said second function input line to said output line, in response to an active signal on said second function enable line.

13. The device of claim 12 wherein said status switching circuit further comprises a third function input line and a third function enable line,

further wherein said status switching circuit drives a signal on said output line inactive, irrespective of said signals on said first function enable line and said second function enable line and connects said third function input line to said output line, in response to an active signal on said third function enable line.

14. The device of claim 10 further comprising a light emitting diode having an input line, wherein said external terminal is coupled to said input line of said light emitting diode.

15. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals for connection to an input/output bus external to said device;

a status indicator terminal; and

a status storage element having an input bit;

wherein said host adapter integrated circuit drives a signal on said status indicator terminal depending on the value of said input bit in said status storage element;

further wherein said signal indicates reset status of said host adapter integrated circuit.

16. The device of claim 15 wherein said signal indicates the status of the use of said input/output bus by said host adapter integrated circuit.

17. The device of claim 15 wherein said host adapter integrated circuit further comprises a system bus module;

and

further wherein said system bus module drives said signal active and drives said signal inactive to indicate the status of the use of said system bus by said host adapter integrated circuit.

30. The device of claims 15, 17, 19, 20, 21 or 22 wherein said host adapter integrated circuit further comprises:

a function enable storage unit; and

a default function storage unit;

further wherein said host adapter integrated circuit suspends driving said signal on said external status indicator terminal and passes a signal from said default function storage unit in response to an inactive signal in said function enable storage unit.

31. The device of claims 15, 17, 19, 20, 21 or 22 further comprising a light emitting diode coupled to said external status indicator terminal.

32. The device of claims 15, 17, 19, 20, 21 or 22 further comprising a logic analyzer coupled to said external status indicator terminal.

18. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals capable of connection to an input/output bus external to said device;

an external status indicator terminal; and

a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said external status indicator terminal depending on the value of said input storage unit in said status storage element;

wherein said input/output bus is a SCSI bus, said host adapter integrated circuit comprises a SCSI module for communication with said SCSI bus, and said SCSI module drives said signal active as long as said SCSI module communicates with said SCSI bus, and otherwise drives said signal inactive.

19. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals capable of connection to an input/output bus external to said device;

an external status indicator terminal; and

a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said external status indicator terminal depending on the value of said input storage unit in said status storage element;

wherein said system bus is a PCI bus, said system bus module drives a first signal to indicate master status and drives a second signal to indicate slave status and said host adapter integrated circuit combines said first signal and said second signal to create said signal on said external status indicator terminal.

20. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals capable of connection to an input/output bus external to said device;

an external status indicator terminal; and

a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said external status indicator terminal depending on the value of said input storage unit in said status storage element;

further wherein said status storage element is accessible by firmware running in said host adapter integrated circuit, and said signal indicates the execution of a predetermined line of said firmware.

28. The device of claims 20, 21 or 22 wherein said host adapter integrated circuit further comprises a chip reset storage unit and further wherein said host adapter integrated circuit suspends driving said signal on said external status indicator terminal in response to an active signal in said chip reset storage unit.

29. The device of claims 20, 21 or 22 wherein said host adapter integrated circuit further comprises a function enable storage unit and further wherein said host adapter integrated circuit suspends driving said signal on said external status indicator terminal in response to an inactive signal in said function enable storage unit.

33. The device of claims 20 or 21 wherein said signal is derived from another signal on said system bus.

21. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals for connection to an input/output bus external to said device;

an external status indicator terminal; and

a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said external status indicator terminal depending on the value of said input storage unit in said status storage element;

wherein said status storage element is in the address space of a processor connected to said system bus; and

further wherein said signal indicates the execution of a predetermined line of software running in said processor.

22. A device comprising:

a system bus;

a host adapter integrated circuit having;

a plurality of system bus terminals connected to said system bus;

a plurality of input/output bus terminals for connection to an input/output bus external to said device;

an external status indicator terminal; and

a status storage element having an input storage unit;

wherein said host adapter integrated circuit drives a signal on said external status indicator terminal depending on the value of said input storage unit in said status storage element;

further wherein said signal is used as a clock signal by said device to clock in identification data for said device from a terminal of said device.

23. A method comprising:

driving a signal on a function input line of a status switching circuit based on the value of an input storage unit in a status storage element;

detecting an active signal on a function disable line of said status switching circuit;

setting the value of said input storage unit in said status storage element;

disconnecting an output line of said status switching circuit from said function input line;

detecting an inactive signal on said function disable line;

connecting said output line to said function input line;

inserting a first write statement at a predetermined location in firmware to set said input storage unit in said status storage element to indicate that the first write statement has been executed; and

inserting a second write statement to clear said input storage unit in said status storage element to indicate that said second write statement has been executed.

24. The method of claim 23 wherein said first write statement indicates the beginning of an idle loop and said second write statement indicates the end of said idle loop.

25. A status indicator circuit comprising:

a status storage element comprising;

a first data input line;

a write address strobe line; and

a first output terminal;

wherein said status storage element latches a signal on said first data input line in response to an active signal on said write address strobe line and supplies said latched signal on said first output terminal; and

a status switching circuit comprising;

a plurality of function input lines, a first function input line of said plurality of function input lines being coupled to said first output terminal of said status storage element;

a first function enable line;

a function disable line;

a default function input line; and

an output line;

wherein said status switching circuit selectively couples and decouples said output line to one of said first function input line and said default function input line in response to a signal on said first function enable line;

further wherein said status switching circuit disconnects said output line from every one of said plurality of function input lines in response to an active signal on said function disable line.

26. The status indicator circuit of claim 25 wherein said first data input line of said status storage element is coupled to a SCSI module, and said SCSI module drives a signal on said first data input line active as long as said SCSI module communicates with a SCSI bus coupled to said SCSI module and otherwise drives said signal inactive.

27. The status indicator circuit of claim 25 wherein said address strobe line of said status storage element is coupled to a line of a PCI bus.

34. The status indicator circuit of claim 27 wherein said status storage element is in the address space of a processor connected to said PCI bus, and wherein a signal on said first function input line indicates execution of a predetermined line of software running in said processor.