Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor

• US 5,657,472 A
• Filed: 03/31/1995
• Issued: 08/12/1997
• Est. Priority Date: 03/31/1995
• Status: Expired due to Term

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Nishtala, Satyanarayana, Coffin, Louis F. III, Narad, Charles E., Kohn, Leslie, Normoyle, Kevin, Van Loo, William C., Ebrahim, Zahir
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/414,922
• Time in Patent Office: 865 Days
• Field of Search: 395/467, 395/468, 395/469, 395/473, 395/477, 395/481, 395/485, 395/449, 395/447
• US Class Current: 711/158
• CPC Class Codes: G06F 12/0828 with concurrent directory accessing, i.e. handling multiple concurrent coherency transactions

Abstract

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.

Claims

1. A computer system, comprising:

a system controller;

a main memory coupled to said system controller; and

a data processor having a cache memory having cache lines for storing data blocks;

said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller;

said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;

said system controller including a corresponding interface coupled to said data processor for receiving memory transaction requests from said data processor, said interface including at least two parallel independent incoming request queues for storing memory transaction requests received from said data processor; and

the system controller including transaction execution logic for executing and responding to the requests in each of its incoming request queues and for ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request.

2. The computer system of claim 1 further including

independent outbound data queues in said data processor, one for each of said transaction classes, for storing data blocks associated with write transaction requests in each respective one of the transaction classes, said outbound data queues filled by said data processor prior to the transmission of the associated memory transaction request to said system controller.

3. The computer system of claim 2 wherein each of said two parallel independent outbound request queues in said data processor is a first-in-first-out buffer for transmitting memory transaction requests to the system controller, said memory transaction request logic, responsive to each of said received transaction requests, generating a reply for transmission to said data processor upon the availability of resources associated with said memory transaction request, said replies strictly ordered in each transaction class such that said data processor receives replies to those of said memory transaction requests transmitted from a transaction class in the same order as the transactions were originally issued from said data processor.

4. The computer system of claim 1 further including:

said data processor including a slave interface, coupled to said system controller, for receiving transaction requests from said system controller, said slave interface including at least one input request queue for storing transaction requests received from said system controller;

said transaction requests including read requests and write requests;

each said transaction request specifying an address for an associated data block to be read or written;

said system controller having a second interface including at least one outbound request queue for storing transaction requests to be transmitted to said data processor'"'"'s slave interface.

5. A computer system, comprising:

a system controller;

a main memory coupled to said system controller; and

a plurality of data processors each having a cache memory having cache lines for storing data blocks;

each said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller;

said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;

said system controller including an interface coupled to each said data processor for sending and receiving memory transaction requests to and from each said data processor, said interface including distinct incoming request queues for each data processor, including at least two parallel independent incoming request queues for each data processor for storing memory transaction requests received from each said data processor; and

said system controller including transaction execution logic for executing said transactions in each of said incoming request queues in the same order that said transactions are stored therein;

said transaction execution logic ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request.

6. The computer system of claim 5,

each data processor including a slave interface, coupled to the system controller, for receiving transaction requests from the system controller, the slave interface including at least one input request queue for storing transaction requests received from the system controller;

the transaction requests including read requests and write requests;

each transaction request specifying an address for an associated data block to be read or written;

the system controller having a second interface for each data processor including at least one output request queue for storing transaction requests to be transmitted to each data processor'"'"'s slave interface, wherein each transaction request to be transmitted corresponds to one of the memory transaction requests received by the system controller from a requesting one of the data processors and has an associated transaction class; and

each slave interface including logic for responding to received transactions requests by generating a reply for transmission to the system controller upon the availability of resources associated with the transaction requests, the replies strictly ordered for each transaction class in the requesting data processors such that the slave interface replies to transaction requests in the same order as the corresponding memory transaction requests were originally stored in their respective outbound request queues by the requesting one of the data processors.

7. The computer system of claim 5, further including

independent outbound data queues in each data processor, one for each of the transaction classes, for storing data blocks associated with write transaction requests in each respective one of the transaction classes, wherein the outbound data queues are filled by their respective data processors prior to the transmission of the associated memory transaction request to the system controller.

8. A method for parallelizing memory transactions in a packet switched cache coherent multiprocessor system having a system controller coupled to a main memory and to a data processor having a cache memory comprising the steps of:

sending memory transaction requests from said data processor to said system controller, including storing said memory transaction requests in at least two parallel independent outbound request queues;

said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;

receiving said memory transaction requests at said system controller and storing said received memory transaction requests in at least two parallel independent incoming request queues, such that said memory transaction requests for each of said transaction classes are stored in distinct ones of incoming request queues; and

processing, at said system controller, each of said memory transaction requests by said data processor, said processing step including executing and responding to the requests in each of its incoming request queues and ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request.

9. The method of claim 8 further including:

for write transaction requests, storing data in independent outbound data queues in said data processor, one for each of said transaction classes, prior to the transmission of the associated write transaction request to said system controller.

10. The method of claim 8, wherein said processing step includes:

in response to each of said received transaction requests, generating a reply for transmission to said data processor upon the availability of resources associated with said memory transaction request, said replies strictly ordered with respect to memory transaction requests in each transaction class such that said data processor receives replies to those of said memory transaction requests transmitted from a transaction class in the same order as the transactions were originally issued from said data processor.

11. The method of claim 8 further including:

receiving at said data processor transaction requests from said system controller corresponding to said memory transaction requests received by said system controller, said transaction requests including read requests and write requests;

each said transaction request specifying an address for an associated data block to be read or written;

said system controller storing in at least one outbound request queue transaction requests to be transmitted to said data processor.

12. A method for parallelizing memory transactions in a packet switched cache coherent multiprocessor system having a system controller coupled to a main memory and to a plurality of data processors each having a cache memory, comprising the steps of:

sending memory transaction requests from each data processor to the system controller, including storing the memory transaction requests in at least two parallel independent outbound request queues;

the memory transaction requests defining at least two transaction classes corresponding to the at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;

receiving the memory transaction requests at the system controller and storing the received memory transaction requests in distinct incoming request queues for each data processor, including at least two parallel independent incoming request queues for each data processor, such that distinct one of the incoming request queues receives memory transaction requests only from a respective one of the data processors and only for a respective one of the transaction classes; and

processing, at the system controller, each of the memory transaction requests by the data processor, the processing step including executing and responding to the requests in each of its incoming request queues and ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request.

13. The method of claim 12, further including:

for write transaction requests generated by each of the data processors, storing data in independent outbound data queues in each data processor, one for each of the transaction classes, prior to the transmission of the associated write transaction request to the system controller.