Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor
First Claim
1. A computer system, comprising:
- a system controller;
a main memory coupled to said system controller; and
a data processor having a cache memory having cache lines for storing data blocks;
said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller;
said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;
said system controller including a corresponding interface coupled to said data processor for receiving memory transaction requests from said data processor, said interface including at least two parallel independent incoming request queues for storing memory transaction requests received from said data processor; and
the system controller including transaction execution logic for executing and responding to the requests in each of its incoming request queues and for ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request.
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Accused Products
Abstract
A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.
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Citations
13 Claims
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1. A computer system, comprising:
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a system controller; a main memory coupled to said system controller; and a data processor having a cache memory having cache lines for storing data blocks; said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller;
said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;said system controller including a corresponding interface coupled to said data processor for receiving memory transaction requests from said data processor, said interface including at least two parallel independent incoming request queues for storing memory transaction requests received from said data processor; and the system controller including transaction execution logic for executing and responding to the requests in each of its incoming request queues and for ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request. - View Dependent Claims (2, 3, 4)
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5. A computer system, comprising:
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a system controller; a main memory coupled to said system controller; and a plurality of data processors each having a cache memory having cache lines for storing data blocks; each said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller;
said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;said system controller including an interface coupled to each said data processor for sending and receiving memory transaction requests to and from each said data processor, said interface including distinct incoming request queues for each data processor, including at least two parallel independent incoming request queues for each data processor for storing memory transaction requests received from each said data processor; and said system controller including transaction execution logic for executing said transactions in each of said incoming request queues in the same order that said transactions are stored therein;
said transaction execution logic ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request. - View Dependent Claims (6, 7)
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8. A method for parallelizing memory transactions in a packet switched cache coherent multiprocessor system having a system controller coupled to a main memory and to a data processor having a cache memory comprising the steps of:
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sending memory transaction requests from said data processor to said system controller, including storing said memory transaction requests in at least two parallel independent outbound request queues;
said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;receiving said memory transaction requests at said system controller and storing said received memory transaction requests in at least two parallel independent incoming request queues, such that said memory transaction requests for each of said transaction classes are stored in distinct ones of incoming request queues; and processing, at said system controller, each of said memory transaction requests by said data processor, said processing step including executing and responding to the requests in each of its incoming request queues and ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request. - View Dependent Claims (9, 10, 11)
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12. A method for parallelizing memory transactions in a packet switched cache coherent multiprocessor system having a system controller coupled to a main memory and to a plurality of data processors each having a cache memory, comprising the steps of:
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sending memory transaction requests from each data processor to the system controller, including storing the memory transaction requests in at least two parallel independent outbound request queues;
the memory transaction requests defining at least two transaction classes corresponding to the at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests;receiving the memory transaction requests at the system controller and storing the received memory transaction requests in distinct incoming request queues for each data processor, including at least two parallel independent incoming request queues for each data processor, such that distinct one of the incoming request queues receives memory transaction requests only from a respective one of the data processors and only for a respective one of the transaction classes; and processing, at the system controller, each of the memory transaction requests by the data processor, the processing step including executing and responding to the requests in each of its incoming request queues and ordering the execution of the requests in accordance with prioritization rules that are independent of the relative order in which an oldest pending request in each of the incoming request queues was received by the system controller, such that a first request in a first one of the incoming request queues may be executed and responded to later than a second request in a second one of the incoming request queues that was received by the system controller later than it received the first request. - View Dependent Claims (13)
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Specification