Memory device with a phase locked loop circuitry

• US 5,657,481 A
• Filed: 11/15/1996
• Issued: 08/12/1997
• Est. Priority Date: 04/18/1990
• Status: Expired due to Term

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): Oberley, Alvin E.
• Assistant Examiner(s): Banankhah, Majid A.
• Application Number:
  US08/749,729
• Time in Patent Office: 270 Days
• Field of Search: 395/550, 395/551, 395/552, 365/230.02, 365/189.06, 365/189.04, 331/1 A, 364/189.06, 364/189.04, 375/113
• US Class Current: 713/400
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A clock signal generation apparatus for a memory device of a data processing system is described for generating an internal clock signal for the memory device that is synchronized with an external clock signal. The data processing system includes a transmission line for transmitting a global clock signal to the memory device. A first receiving circuit is coupled to a first point of the transmission line for receiving the global clock signal at the first point and for generating a first local clock signal. A first delay circuitry delays the first local clock signal to be a first delayed clock signal such that the first delayed local clock signal is synchronized with the global clock signal received at the first point of the transmission line. The first delay circuitry provides a first variable delay to the first delayed local clock signal. A second receiving circuit is coupled to the second point of the transmission line for receiving the global clock signal at the second point and for generating a second local clock signal. A second delay circuitry delays the second local clock signal to be a second delayed clock signal such that the second delayed local clock signal is synchronized with the global clock signal received at the second point of the transmission line. The second delay circuitry provides a second variable delay to the second delayed local clock signal. A third delay circuitry is coupled to receive the first and second local clock signals for generating the internal clock signal for the memory device at a timing that is halfway between the first and second local clock signals.

Claims

1. A memory device, comprising:

(A) a memory array that stores data at addresses;

(B) interface circuitry coupled to the memory array, wherein the data is transferred between the interface circuitry and the memory array;

(C) a clock signal receiving circuit coupled to receive an external clock signal, the clock signal receiving circuit generating a local clock signal; and

(D) phase locked loop circuitry coupled to the clock signal receiving circuit and the interface circuitry, the phase locked loop circuitry receiving the local clock signal and providing a variable delay to the local clock signal to generate a delayed local clock signal that is synchronized with the external clock signal, wherein the delayed local clock signal is coupled to the interface circuitry, and wherein the memory array, the interface circuitry, the clock signal receiving circuit, and the phase locked loop circuitry all reside on a single semiconductor substrate.

2. The memory device of claim 1, wherein the memory array is a dynamic random access memory (DRAM).

3. The memory device of claim 1, wherein the external clock signal received by the clock signal receiving circuit is a low-voltage-swing clock signal, wherein the local clock signal is a full-voltage-swing clock signal, wherein the clock signal receiving circuit further comprises a DC amplifier circuit for amplifying the low-voltage-swing external clock signal in order to output the full-voltage-swing local clock signal.

4. A computer system, comprising:

(A) a bus;

(B) a bus master coupled to the bus;

(C) a memory device coupled to the bus, wherein the memory device comprises;

(i) a memory array that stores data at addresses;

(ii) interface circuitry coupled to the memory array, wherein the data is transferred between the interface circuitry and the memory array;

(iii) a clock signal receiving circuit coupled to receive an external clock signal, the clock signal receiving circuit generating a local clock signal; and

(iv) phase locked loop circuitry coupled to the clock signal receiving circuit and the interface circuitry, the phase locked loop circuitry receiving the local clock signal and providing a variable delay to the local clock signal to generate a delayed local clock signal that is synchronized with the external clock signal, wherein the delayed local clock signal is coupled to the interface circuitry.

5. The computer system of claim 4, wherein the memory array is a dynamic random access memory (DRAM).

6. The computer system of claim 4, wherein the external clock signal received by the clock signal receiving circuit is a low-voltage-swing clock signal, wherein the local clock signal is a full-voltage-swing clock signal.

7. The computer system of claim 6, wherein the dock signal receiving circuit further comprises a DC amplifier circuit for amplifying the low-voltage-swing external clock signal in order to output the full-voltage-swing local clock signal.

18. The computer system of claim 4, wherein the memory array, the interface circuitry, the clock signal receiving circuit, and the phase locked loop circuitry all reside on a single semiconductor substrate.

8. A memory device comprising:

a memory array;

interface circuitry coupled to the memory array, wherein data is transferred between the interface circuitry and the memory array;

a first clock signal receiving circuit coupled to receive an external clock signal, the first clock signal receiving circuit generating a first local clock signal;

first phase locked loop circuitry coupled to the interface circuitry and the first clock signal receiving circuit, the first phase locked loop circuitry including a first input receiver receiving and sampling the external clock signal;

wherein the first phase locked loop circuitry receives the first local clock signal and provides a first variable delay to the first local clock signal to generate a first delayed local clock signal, wherein the first delayed local clock signal is coupled to the interface circuitry and controls operations with respect to the interface circuitry;

wherein the first phase locked loop circuitry provides a first fixed delay to the first delayed local clock signal to generate a fixed delayed local clock signal, wherein the fixed delayed local clock signal is coupled to the first input receiver; and

wherein the first phase locked loop circuitry adjusts the first variable delay based on the sampled external clock to a first value such that the fixed delayed local clock signal is synchronized with the external clock signal, but a transition of the fixed delayed local clock signal precedes a transition of the external dock signal by a first amount of time equal to a delay of the first input receiver.

9. The memory device of claim 8, further comprising:

second phase locked loop circuitry coupled to the first phase locked loop circuitry and including a second input receiver receiving and sampling the external clock signal;

wherein the second phase locked loop circuitry receives the first delayed local signal and provides a second variable delay to the first delayed local clock signal to generate a second delayed local clock signal, wherein the second delayed local clock signal is coupled to the second input receiver; and

wherein the second phase locked loop circuitry adjusts the second variable delay to a second value such that the second delayed local clock signal is synchronized with the external clock signal, but a transition of the second delayed local clock signal precedes a transition of the external clock signal by a second amount of time equal to a delay of the second input receiver.

10. The memory device of claim 9, further comprising:

a delay circuit coupled to the first phase locked loop circuitry the interface circuitry, and the second phase locked loop circuitry, the delay circuit receiving the first delayed local clock signal and providing a third variable delay to the first delayed local signal to generate a third delayed local clock signal at a time that is halfway between the fixed delayed local clock signal and the second delayed local clock signal, wherein the third delayed local clock signal is coupled to the interface circuitry.

11. The memory device of claim 8, wherein the first input receiver comprises a sense amplifier.

12. The memory device of claim 9, wherein:

the first input receiver comprises a first sense amplifier; and

the second input receiver comprises a second sense amplifier.

13. A memory device, comprising:

a memory array that stores data at addresses;

interface circuitry coupled to the memory array, wherein data is transferred between the interface circuitry and the memory array;

a clock signal receiving circuit coupled to receive an external clock signal, the clock signal receiving circuit generating a local clock signal;

phase locked loop circuitry coupled to the clock signal receiving circuit and the interface circuitry, the phase locked loop circuitry receiving and sampling the external clock signal;

wherein the phase locked loop circuitry receives the local dock signal and provides a variable delay to the local clock signal to generate a delayed local clock signal, wherein the delayed local clock signal is coupled to the interface circuitry; and

wherein the phase locked loop circuitry adjusts the variable delay based on the sampled external clock to a value such that the delayed local clock signal and the external clock signal are synchronized and have a controlled phase relationship.

14. A memory device in a computer system having a multiline bus, comprising:

a memory array;

a receiver circuit coupled to the memory array and the multiline bus of the computer system, the receiver circuit receiving data, addresses, and control information that are time multiplexed on the multiline bus;

a first clock signal receiving circuit that receives an external clock signal and generates a first local clock signal; and

first phase locked loop circuitry coupled to the first clock signal receiving circuit and the receiver circuit, wherein the first phase locked loop circuitry receives the first local clock signal and provides a first variable delay to the first local clock signal to generate a first delayed local clock signal, wherein the first delayed local clock signal controls operations with respect to the receiver circuit and is synchronized with the external clock signal.

15. The memory device of claim 14, wherein the multiline bus has a total number lines less than a total number of bits in any single address.

16. The memory device of claim 14, wherein the multiline bus includes a transmission line for transmitting the external clock signal to the memory device, wherein the first dock signal receiving circuit is coupled at a first point of the transmission line.

17. The memory device of claim 16, further comprising:

second phase locked loop circuitry coupled to the first phase locked loop circuitry, wherein the second phase locked loop circuitry is coupled to the transmission line at a second point and receives the external clock signal at the second point, wherein the second phase locked loop circuitry receives the first delayed local clock signal and provides a second variable delay to the first delayed local clock signal to generate a second delayed local dock signal such that the second delayed local dock signal is synchronized with the external clock signal received at the second point of the transmission line; and

a delay circuit coupled to the first phase locked loop circuitry, the receiver circuit, and the second phase locked loop circuitry, wherein the first phase locked loop circuitry provides a first fixed delay to the first delayed local clock signal to generate a fixed delayed local dock signal, and wherein the delay circuit receives the first delayed local clock signal and provides a third variable delay to the first delayed local dock signal to generate a third delayed local dock signal at a time that is halfway between the fixed delayed local clock signal and the second delayed local clock signal, wherein the third delayed local clock signal is coupled to the receiver circuit.