Analog-to-digital converter and output driver

• US 5,659,261 A
• Filed: 05/13/1996
• Issued: 08/19/1997
• Est. Priority Date: 10/30/1991
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Chi, Chong In, Fisher, Gregory James, Bacrania, Kantilal
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): Ton, My Trang Nu
• Application Number:
  US08/645,139
• Time in Patent Office: 463 Days
• Field of Search: 307/253, 307/254, 307/270, 307/570, 307/261, 307/433, 307/100, 307/108, 307/112, 307/375, 327/427, 327/432, 327/436, 327/437, 327/478, 327/482, 326/83, 326/91
• US Class Current: 327/112
• CPC Class Codes: G05F 3/262 using field-effect transistors only
• CPC Class Codes: G05F 3/30 Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities G05F3/26 takes precedence
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H01L 27/0214 for internal polarisation, e.g. I2L
• CPC Class Codes: H01L 27/0623 in combination with bipolar transistors
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H03F 1/523 for amplifiers using field-effect devices H03F1/526 takes precedence
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 3/505 with field-effect devices
• CPC Class Codes: H03G 1/0082 using bipolar transistor-type devices
• CPC Class Codes: H03K 17/223 in field-effect transistor switches
• CPC Class Codes: H03K 5/15 Arrangements in which pulses are delivered at different times at several outputs, i.e. pulse distributors distributing, switching or gating arrangements H03K17/00
• CPC Class Codes: H03M 1/162 the steps being performed sequentially in a single stage, i.e. recirculation type H03M1/161 takes precedence
• CPC Class Codes: H03M 1/365 the voltage divider being a single resistor string

Abstract

The A-to-D converter 300 has an output buffer 320 with fourteen drivers each the same as driver 4100. Driver 4100 includes bipolar pull up pull down transistors 4102, 4103. Those transistors are both coupled to an output. Pull up transistor 4102 is coupled to a first reference voltage VDD; pull down transistor 4103 is coupled to a second or ground reference potential. A base drive circuit comprising a series connection between a resistor and a transistor 4121 to provide additional current to saturate the pull down transistor 4103 and thereby lower the collector-to-emitter voltage drop of transistor 4103 when transistor 4103 is turned on.

Claims

1. A driver, comprising:

(a) an input node for receiving an input signal;

(b) an output node for providing an output signal representative of the input signal;

(c) first and second reference nodes for connection respectively to first and second reference voltages;

(d) first and second output bipolar transistors, the first output transistor coupled between the output and the first reference node and the second output transistor coupled between the output and the second reference node;

(e) base drive circuitry connected to the base of said second bipolar output transistor for driving said second bipolar output transistor into saturation.

2. The driver of claim 1, wherein:

(a) said base drive circuitry includes a resistor and NMOS transistor connected in series with each other for selectively coupling said base of said second bipolar output transistor to the first reference node.

3. The driver of claim 2, further comprising:

a diode between said base of said second output bipolar transistor and said output node and oriented for current flow from said output node to said base of said first output bipolar transistor.

4. The driver of claim 1, further comprising:

(a) an enable node for receiving an enabling signal; and

(b) enable circuitry coupled to said enable node for isolating said output node from all potentials at said input node in response to a signal at said enabling node.

5. The driver of claim 1, wherein:

said first reference node is a 5 volt power supply; and

said second reference node is ground.

6. The driver of claim 1, wherein:

said second reference node is ground; and

said second bipolar transistor is an NPN transistor with emitter connected to ground and collector connected to said output node through a resistor.

7. An integrated circuit output driver, comprising:

a first and second power rails;

an output node;

a first bipolar transistor with collector coupled to said first power rail and emitter coupled to said output node;

a second bipolar transistor with collector coupled to said output node and emitter coupled to said second power rail;

an input node; and

a current source controlled by signals at said input node and connected to the base of said second bipolar transistor, wherein said current source forward biases the collector base junction of said second bipolar transistor when said input turns on said second bipolar transistor and thereby drives said second transistor into saturation and provides for a voltage difference between said output node and said second power rail of magnitude at most about 0.2 volt.

8. The driver of claim 7, wherein:

said current source includes a resistor and NMOS transistor in series coupling said base of said second bipolar transistor to said first power rail.

9. A method of driving output bipolar transistors, comprising the steps of:

providing first and second bipolar transistors, the first bipolar transistor with its collector coupled to a first power rail and its emitter coupled to an output node and the second bipolar transistor with its collector coupled to the output node, its emitter coupled to a reference potential, and its base coupled to an input node;

providing a switchable current source connected to said base of the second bipolar transistor;

switching said current source on to saturate said second bipolar transistor when said output node is to be driven to said reference potential.