Signal evaluation circuit for a motion detector

• US 5,659,316 A
• Filed: 11/15/1995
• Issued: 08/19/1997
• Est. Priority Date: 03/24/1994
• Status: Expired due to Fees

• Current Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Original Assignee: Cerberus ABP Investor LLC (Cerberus Capital Management LP)
• Inventors: Stierli, Peter
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/545,685
• Time in Patent Office: 643 Days
• Field of Search: 341/143, 341/155, 341/140, 128/782
• US Class Current: 341/143
• CPC Class Codes: G08B 13/19 using infrared-radiation detection systems G08B13/194 takes precedence
• CPC Class Codes: G08B 29/26 by updating and storing reference thresholds

Abstract

The motion detector generates a sensor signal (SS) which contains a direct current portion and an alternating current portion. The signal evaluation circuit (3) contains means for filtering out the direct current portion, an analogue-to-digital converter (4) and an amplifier for the alternating current portion of the sensor signal. The analogue-to-digital converter (4) is provided for the direct digitizing of the entire sensor signal (SS) and the means for filtering out the direct current portion are formed by a digital high-pass filter (5) connected downstream of the analogue-to-digital converter.

Claims

1. A signal evaluation circuit for a motion detector in which an output signal from an infrared sensor has a relatively large direct current component and a small alternating current component, comprising:

an analog-to-digital converter for digitizing the sensor signal to form a digitized signal;

a digital high-pass filter operatively coupled to the analog-to-digital converter for filtering out the direct current component from the digitized signal; and

an amplifier operatively coupled to the digital high-pass filter for amplifying the alternating current component.

2. The signal evaluation circuit according to claim 1, wherein the analog-to-digital converter comprises a sigma-delta structure.

3. The signal evaluation circuit according to claim 2, wherein the sigma-delta structure comprises a sigma-delta loop and a decimator operatively coupled to an output of the sigma-delta loop.

4. The signal evaluation circuit according to claim 3, wherein the decimator comprises a counter.

5. The signal evaluation circuit according to claim 3 or 4, wherein the sigma-delta loop comprises:

an integrator;

a comparator connected to an output of the integrator; and

a 1-bit digital-to-analog converter operatively coupled to an output of the comparator, for being clocked by an output signal from the comparator, and for optionally feeding back to the integrator one of two voltages, thereby to establish a range for an integrator output signal.

6. The signal evaluation circuit according to claim 5, wherein the integrator comprises an operational amplifier.

7. The signal evaluation circuit according to claim 3 or 4, wherein the decimator comprises an accumulator for accumulating output signal bits from the sigma-delta loop in a parallel word having a preset width.

8. The signal evaluation circuit according to claim 7, wherein the digital high-pass filter comprises a discriminator for choosing from the parallel word a reduced word which comprises a reduced number of lowest bits of the parallel word.

9. The signal evaluation circuit according to claim 8, wherein the discriminator comprises means for triggering an alarm when a signal represented by the reduced word exceeds a threshold.

10. A signal evaluation circuit for a motion detector in which an output signal from a motion sensor has a relatively large direct current component and a small alternating current component, comprising:

an analog-to-digital converter comprising a sigma-delta structure, for digitizing the sensor signal to form a digitized signal;

a digital high-pass filter operatively coupled to the analog-to-digital converter for filtering out the direct current component from the digitized signal; and

an amplifier operatively coupled to the digital high-pass filter for amplifying the alternating current component.

11. The signal evaluation circuit according to claim 10, wherein the sigma-delta structure comprises a sigma-delta loop and a decimator operatively coupled to an output of the sigma-delta loop.

12. The signal evaluation circuit according to claim 11, wherein the decimator comprises a counter.

13. The signal evaluation circuit according to claim 10 or 11, wherein the sigma-delta loop comprises:

an integrator;

a comparator connected to an output of the integrator; and

a 1-bit digital-to-analog converter operatively coupled to an output of the comparator, for being clocked by an output signal from the comparator, and for optionally feeding back to the integrator one of two voltages, thereby to establish a range for an integrator output signal.

14. The signal evaluation circuit according to claim 13, wherein the integrator comprises an operational amplifier.

15. The signal evaluation circuit according to claim 10 or 11, wherein the decimator comprises an accumulator for accumulating output signal bits from the sigma-delta loop in a parallel word having a preset width.

16. The signal evaluation circuit according to claim 15, wherein the digital high-pass filter comprises a discriminator for choosing from the parallel word a reduced word which comprises a reduced number of lowest bits of the parallel word.

17. The signal evaluation circuit according to claim 16, wherein the discriminator comprises means for triggering an alarm when a signal represented by the reduced word exceeds a threshold.