Monolithic PC audio circuit with enhanced digital wavetable audio synthesizer

• US 5,659,466 A
• Filed: 11/02/1994
• Issued: 08/19/1997
• Est. Priority Date: 11/02/1994
• Status: Expired due to Term

• Current Assignee: Microsemi Semiconductor (U.S.) Inc. (Microchip Technology Incorporated)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hogan, Michael, Hewitt, Larry D., Gulick, Dale E., Norris, David, Brehmer, Geoffrey E., Suggs, David N., Blumenthal, Jeffrey M., Soques, Martin P., Linz, Alfredo R., Brown, Glen W., Schnizlein, Paul G., Guercio, David, Cabler, Carlin Dru, Torok, Alan T., Feemster, Ryan, Spak, Michael E.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): PEESO, THOMAS R
• Application Number:
  US08/333,536
• Time in Patent Office: 1,021 Days
• Field of Search: 84/604, 84/610, 84/606, 84/602, 84/603, 395/650, 395/500, 364/410, 364/514 R
• US Class Current: 700/94
• CPC Class Codes: G06F 3/162 Interface to dedicated audio devices, e.g. audio drivers, interface to CODECs
• CPC Class Codes: G10H 1/0066 using a MIDI interface
• CPC Class Codes: G10H 1/125 using a digital filter
• CPC Class Codes: G10H 2230/035 Power management, i.e. specific power supply solutions for electrophonic musical instruments, e.g. auto power shut-off, energy saving designs, power conditioning, connector design, avoiding inconvenient wiring
• CPC Class Codes: G10H 2240/311 MIDI transmission G10H2240/056 takes precedence
• CPC Class Codes: G10H 2250/191 Chebyshev polynomials, e.g. to provide filter coefficients for sharp rolloff filters
• CPC Class Codes: G10H 2250/545 Aliasing, i.e. preventing, eliminating or deliberately using aliasing noise, distortions or artifacts in sampled or synthesised waveforms, e.g. by band limiting, oversampling or undersampling, respectively
• CPC Class Codes: G10H 2250/571 Waveform compression, adapted for music synthesisers, sound banks or wavetables
• CPC Class Codes: G10H 2250/611 Waveform decimation, i.e. integer division of the sampling rate for reducing the number of samples in a discrete-time signal, e.g. by low-pass anti-alias filtering followed by the actual downsampling
• CPC Class Codes: G10H 7/002 using a common processing for different operations or calculations, and a set of microinstructions (programme) to control the sequence thereof
• CPC Class Codes: H03K 23/68 with a base which is a non-integer

Abstract

A digital wavetable audio synthesizer is described. The synthesizer can generate up to 32 high-quality audio digital signals or voices, including delay-based effects, at either a 44.1 KHz sample rate or at sample rates compatible with a prior art wavetable synthesizer. The synthesizer includes an address generator which has several modes of addressing wavetable data. The address generator'"'"'s addressing rate controls the pitch of the synthesizer'"'"'s output signal. The synthesizer performs a 10-bit interpolation, using the wavetable data addressed by the address generator, to interpolate additional data samples. When the address generator loops through a block of data, the signal path interpolates between the data at the end and start addresses of the block of data to prevent discontinuities in the generated signal. A synthesizer volume generator, which has several modes of controlling the volume, adds envelope, right offset, left offset, and effects volume to the data. The data can be placed in one of sixteen fixed stereo pan positions, or left and right offsets can be programmed to place the data anywhere in the stereo field. The left and right offset values can also be programmed to control the overall volume. Zipper noise is prevented by controlling the volume increment. A synthesizer LFO generator can add LFO variation to: (i) the wavetable data addressing rate, for creating a vibrato effect; and (ii) a voice'"'"'s volume, for creating a tremolo effect. Generated data to be output from the synthesizer is stored in left and right accumulators. However, when creating delay-based effects, data is stored in one of several effects accumulators. This data is then written to a wavetable. The difference between the wavetable write and read addresses for this data provides a delay for echo and reverb effects. LFO variations added to the read address create chorus and flange effects. The volume of the delay-based effects data can be attenuated to provide volume decay for an echo effect. After the delay-based effects

Claims

1. A monolithic integrated circuit for providing audio enhancement for a host personal computer of the type including a central processor, system memory and a system bus for transferring data, control and address signals within the system, said monolithic integrated circuit comprising:

a system control module for providing an interface to the system bus, said control module further including;

a register data bus for distributing data throughout said integrated circuit and in communication with system bus decoding circuitry;

interrupt signal control;

a plurality of integrated circuit control registers; and

internal clock generation and control circuits;

a digital output terminal for transmitting digital signals to external devices;

a digital wavetable audio synthesizer module for generating digital audio signals;

said synthesizer module further including;

a digital signal transfer circuit for transferring synthesized digital audio signals to said output terminal; and

a data input circuit for acquiring audio signal data from one or more external memory devices; and

a local memory control module for interfacing said integrated circuit with external memory devices;

said memory control module being in communication with said register data bus for transferring data between said synthesizer module, or said system control module, and external memory devices.

2. The circuit of claim 1, further comprising:

a game port module, said game port module including;

an analog input circuit for receiving game control signals from external devices;

an analog-to-digital conversion circuit for converting analog input signals to digital signals; and

an interface circuit for providing communication between said register data bus and said analog input circuit and said conversion circuit.

3. The circuit of claim 1, further comprising a musical instrument digital interface module for providing data communication between said register data bus and external devices.

4. The circuit of claim 1, wherein said local memory control module includes a memory interface circuit for generating address and control signals for enabling data transfer between said integrated circuit and external memory devices.

5. The circuit of claim 4, wherein said memory interface circuit includes means for interfacing with external random access and read only memory devices.

6. A monolithic integrated circuit for providing audio enhancement for a host personal computer of the type including a central processor, system memory and a system bus for transferring data, control and address signals within the system, said monolithic integrated circuit comprising:

a system control module for providing an interface to the system bus, said control module further including;

a register data bus for distributing data throughout said integrated circuit and in communication with system bus decoding circuitry;

interrupt signal control;

a plurality of integrated circuit control registers; and

internal clock generation and control circuits;

synthesizer digital-to-analog conversion circuitry for providing digital-to-analog signal conversion;

said synthesizer digital-to-analog conversion circuitry further including;

an analog output terminal for transmitting analog signals to external devices; and

a digital audio signal input circuit for receiving digital audio signals;

a digital wavetable audio synthesizer module for generating digital audio signals;

said synthesizer module further including;

a digital signal transfer circuit for transferring synthesized digital audio signals to said synthesizer digital-to-analog signal conversion circuitry; and

a data input circuit for acquiring audio signal data from one or more external memory devices; and

a local memory control module for interfacing said integrated circuit with external memory devices;

said memory control module being in communication with said register data bus for transferring data between said synthesizer module, said synthesizer digital-to-analog conversion circuitry or said system control module, and external memory devices.

7. The circuit of claim 6, further comprising:

a game port module, said game port module including;

an analog input circuit for receiving game control signals from external devices;

an analog-to-digital conversion circuit for converting analog input signals to digital signals; and

an interface circuit for providing communication between said register data bus and said analog input circuit and said conversion circuit.

8. The circuit of claim 6, further comprising a musical instrument digital interface module for providing data communication between said register data bus and external devices.

9. The circuit of claim 6, wherein said local memory control module includes a memory interface circuit for generating address and control signals for enabling data transfer between said integrated circuit and external memory devices.

10. The circuit of claim 9, wherein said memory interface circuit includes means for interfacing with external random access and read only memory devices.