Memory test system having a pattern generator for a multi-bit test

• US 5,659,549 A
• Filed: 08/26/1996
• Issued: 08/19/1997
• Est. Priority Date: 08/31/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Oh, Sang-Chul, Cho, Sung-Bum
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/702,929
• Time in Patent Office: 358 Days
• Field of Search: 371/21.3, 371/21.2, 371/21.6, 371/27, 365/201, 324/158 R
• US Class Current: 714/720
• CPC Class Codes: G11C 29/56 External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor

Abstract

A semiconductor memory testing methods and apparatus are arranged to accommodate a multi-bit mode of testing operation in which the memory under test itself includes internal peripheral circuits for comparing the contents of memory cells for multi-bit testing, and outputting a single-bit indicative of whether or not said multiple cells have the same state. The present invention includes methods and apparatus for determining the polarity of a memory cell under test, and taking that polarity into account informing expected data to be compared to the output of the memory under test.

Claims

1. A semiconductor memory test system, comprising:

an address generator for generating an address signal and supplying said generated address signal to a memory under test;

a data generator for generating test data and supplying said generated test data to the memory under test;

a clock generator for providing a clock signal to the address generator and to the memory under test;

a controller for controlling and coordinating operation of the address generator, the data generator and the clock generator for writing the test data into and reading the test data out from the memory under test;

a logic comparator for comparing an output of the memory under test with expected data, for determining whether the memory under test functions correctly; and

a logic circuit coupled to receive the test data and a multi-bit test control signal asserted during multi-bit testing for providing said expected data to the logic comparator responsive to assertion of the multi-bit test control signal.

2. A semiconductor memory test system according to claim 1 wherein the logic circuit includes a logic OR-gate having a first input connected to the data generator and a second input connected to receive the multi-bit test control signal and an output connected to the logic comparator, so that the logic-OR gate effectively complements the test data provided to the memory under test when the multi-bit test control signal is in a logic "1" state.

3. A semiconductor memory test system according to claim 1 further comprising cell polarity logic means coupled to the address generator for determining and indicating a polarity of a memory cell corresponding to the address signal as being either true or complementary.

4. A semiconductor memory test system according to claim 3 wherein the logic circuit includes first logic means coupled to the data generator to receive the test data and coupled to the cell polarity logic means to receive an indication of the corresponding cell polarity;

second logic means coupled to the first logic means and coupled to receive the multi-bit test control signal; and

third logic means coupled to the second logic means to provide the expected data whereby the expected data has a predetermined logic state when the test data and the cell polarity have selected states and the multi-bit test control signal is asserted.

5. A semiconductor memory test system according to claim 3 wherein the logic circuit includes:

a first XOR gate coupled to the data generator to receive the test data and coupled to the cell polarity logic means to receive an indication of the corresponding cell polarity;

a second XOR gate coupled to the first XOR gate and coupled to receive the multi-bit test control signal; and

a third XOR gate coupled to the second XOR gate to provide the expected data to the logic comparator, whereby the expected data has a predetermined logic state when the test data and the cell polarity have selected states and the multi-bit test Control signal is asserted.

6. A semiconductor memory test system according to claim 3 further comprising test bit logic means (26) arranged for combining the test data and the indication of the corresponding memory cell polarity to form a test bit for storage in the memory under test;

and wherein the cell polarity logic means provides a logic "0" when the cell polarity is true and provides a logic "1" when the corresponding cell polarity is complementary; and

wherein the logic circuit includes;

a first XOR gate coupled to the data generator and coupled to the cell polarity logic means to receive an indication of the corresponding cell polarity, so as to output a logic "0" signal when a logic "0" test bit is generated and the corresponding memory cell has true polarity, or a logic "1" test bit is generated and the corresponding memory cell has complementary polarity;

a second XOR gate coupled to the first XOR gate and coupled to receive the multi-bit test control signal so as to output a logic "1" when the first XOR output is a logic "0" and the multi-bit test control signal is a logic "1"; and

a third XOR gate coupled to the second XOR gate and coupled to the to provide a logic "1" as the expected data to the logic comparator, for comparison to a logic "1" output by the memory under test when all of the test bits read out from the memory cells in a multi-bit test have the same state.

7. A semiconductor memory test system according to claim 3 wherein the cell polarity logic means (30) provides a logic "0" when the corresponding cell polarity is true and provides a logic "1" when the corresponding cell polarity is complementary, and further comprising:

test bit logic means (26) arranged for combining the test data and the indication of the corresponding memory cell polarity so as to form a complemented test bit (14) for writing into the memory under test when the corresponding cell polarity is complementary; and

wherein the logic circuit includes;

control logic means coupled to the data generator and coupled to the cell polarity logic means to receive an indication of the corresponding cell polarity, so as to output a multi-bit test control signal (MBT1) having a logic "0" signal when a logic "0" test bit is generated and the corresponding memory cell has true polarity, or a logic "1" test bit is generated and the corresponding memory cell has complementary polarity; and

a logic OR-gate (50) having a first input connected to receive the complemented test bit and a second input connected to receive the multi-bit test control signal, and having an output connected to the logic comparator (15) to provide the expected data (ED) signal.

8. A method of testing a semiconductor memory device under test (MUT) having an on-board multi-bit test logic circuit that outputs a memory output bit having a predetermined logic state when all of the bits read out of a selected group of cells in the memory device have the same logic state, the method comprising the steps of:

generating a current address for accessing a selected group of cells in the MUT;

generating a test bit;

determining whether the current address corresponds to a true polarity memory cell or to a complement polarity memory cell;

if the current address corresponds to a complementary polarity memory cell, complementing the test bit to form a pattern generator output bit;

if the current address corresponds to a true polarity memory cell, providing the test bit as the pattern generator output bit;

writing the pattern generator output bit to all of the selected group of cells in the MUT;

reading the memory output bit to determine whether or not all of the bits read out of the selected group of cells in the memory device have the same logic state;

forcing the expected data bit ED to a selected state; and

comparing the memory output bit to the expected data bit to determine whether the MUT has a defect among the selected group of cells.

9. A method according to claim 8 wherein said forcing the expected data bit ED to a selected state includes forcing the ED to the said predetermined logic state assumed by the MUT test bit when all of the bits read out of the selected group of cells in the memory device have the same logic state.

10. A method according to claim 8 wherein said forcing the expected data bit ED to a selected state includes forcing the ED to a complement of the predetermined logic state assumed by the MUT test bit when all of the bits read out of the selected group of cells in the memory device have the same logic state.

11. A test bit pattern generator for use in testing a semiconductor memory device comprising:

an address generator for generating an address signal for addressing a memory device under test;

a data generator for generating test data to write into the memory under test;

a clock generator for clocking said memory under test and the address generator;

a controller for controlling said address generator, said data generator and said clock generator for writing the test data into and reading the test data out from the memory under test;

expected data (ED) means for forming expected data responsive to both the test data and the address signal for comparison to the data read out of the memory under test.

12. A test bit pattern generator according to claim 11 wherein the expected data means including means for complementing the test data when the address signal corresponds to a cell location in the memory having a selected polarity.