Method and apparatus for coherent reception in a spread-spectrum receiver

• US 5,659,573 A
• Filed: 10/04/1994
• Issued: 08/19/1997
• Est. Priority Date: 10/04/1994
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Ling, Fuyun, Bruckert, Eugene J.
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US08/317,501
• Time in Patent Office: 1,050 Days
• Field of Search: 375/355, 375/200, 375/205, 375/206, 375/207, 375/208, 375/365, 375/366, 375/260, 375/267, 375/344, 375/347, 375/367, 375/376, 370/18, 370/19, 370/100.1, 370/105.4, 370/105.5, 455/132-135, 455/137, 455/139
• US Class Current: 375/142
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7087 Carrier synchronisation aspects
• CPC Class Codes: H04B 1/7117 Selection, re-selection, allocation or re-allocation of paths to fingers, e.g. timing offset control of allocated fingers
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04B 2201/70705 Rate detection
• CPC Class Codes: H04J 3/0605 Special codes used as synchronising signal
• CPC Class Codes: H04L 25/0202 Channel estimation
• CPC Class Codes: H04L 27/2276 using frequency multiplication or harmonic tracking

Abstract

A method and apparatus is provided for facilitating coherent communication reception. A received reference symbol coded spread spectrum communication signal is despread with a spreading code to derive a stream of reference samples and a stream of data samples. The channel response is estimated by utilizing the stream of reference samples. An offset frequency detector determines an offset to be applied to the received signal via a frequency locked loop, while a timing control compensates for slow timing drift and fast fading based on power estimates derived from the stream of reference samples and/or the stream of data samples. A slot detector controls gates which optimize the timing control and frequency offset detector outputs from the various timing branches. Thus an improved detection of estimated data symbols from the stream of received data samples is provided.

Claims

1. A coherent spread spectrum receiver, including a sampler for digitizing a received spread spectrum signal and a despreader following the sampler for despreading the received digitized spread spectrum signal into a data signal, comprising:

(a) extracting means coupled to the despreader for extracting reference sample information from the data signal;

(b) timing control means coupled to the extracting means for adjusting the timing of the received spread spectrum signal based on at least one of the data signal and the reference sample information; and

(c) frequency offset means coupled to the extracting means for adjusting one of the group consisting of the phase and frequency of the received spread spectrum signal.

2. The receiver of claim 1, wherein the data signal is a time division multiplexed signal, and the receiver further comprises a slot detector means, coupled to the extracting means and timing control means, for controlling the frequency offset means to only adjust the one of the group consisting of the phase and frequency of the received spread spectrum signal for an occupied slot.

3. The receiver of claim 1, wherein the timing control means further comprises a power estimator means coupled to the extractor means for determining a first power estimate based on at least one of the data signal and the reference sample information, and a timing controller operable for adjusting the timing of the received spread spectrum signal based on the power estimate.

4. The receiver of claim 3, wherein the despreader, extracting means and power estimator means together comprise an early timing branch for receiving an early replica of the received spread spectrum signal;

the receiver further comprises a late timing branch for receiving a late replica of the received spread spectrum signal, the late timing branch comprising a further despreader for despreading the received spread spectrum signal into a late replica data signal, a further extracting means for extracting late replica reference sample information from the late replica data signal, and a further power estimator means for determining a second power estimate based on at least one of the late replica data signal and the late replica reference sample information, the further power estimator also being coupled to the timing controller; and

wherein the timing controller comprises at least one of the group consisting of a delay-locked loop means for adjusting an output timing of the sampler based on the first and second power estimates, and a selector means for controlling a gate coupled between a coherent detector on the one hand and the despreader and further despreader on the other hand to connect one of the despreader and further despreader to the coherent detector based on the first and second power estimates.

5. The receiver of claim 4, wherein the delay-locked loop means comprises a differencer means for calculating the power difference between the first and second power estimates.

6. The receiver of claim 5, wherein the sampler comprises an analog to digital converter (A/D), and a buffer means, coupled between the A/D and the early and late timing branches and also coupled to the delay-locked loop means, for adjusting an output timing of the received spread spectrum signal and the late replica of the received spread spectrum signal from the buffer means to the early and late timing branches based on the calculated power difference from the differencer.

7. The receiver of claim 4, further comprising a middle timing branch coupled to the sampler for receiving a third replica of the received spread spectrum signal, the middle timing branch comprising a third despreader for despreading the received spread spectrum signal into a third replica data signal, a third extracting means for extracting third replica reference sample information from the third replica data signal, and a third power estimator means for determining a third power estimate based on at least one of the third replica data signal and the third replica reference sample information, the third power estimator also being coupled to the timing controller;

and

wherein the selector means comprises a comparator means for determining a greatest one of the first, second and third power estimates and controlling the gate to connect a corresponding one of the early, middle and late timing branches, with the greatest one of the first, second and third power estimates, to the coherent detector.

8. A synchronization device for use in a coherent direct sequence spread-spectrum receiver, comprising an extractor operable for extracting timing information from a received reference symbol coded spread-spectrum signal, wherein the extractor comprises:

(a) a first despreading means for despreading an advanced replica of the received reference symbol coded spread-spectrum signal with a despreading signal to form an early despread signal;

(b) a second despreading means for despreading a retarded replica of the received reference symbol coded spread-spectrum signal with a despreading signal to form a late despread signal;

(c) reference sample extracting means for extracting reference samples from the early and the late despread signal;

(d) correlating means for correlating the reference samples from the early despread signal with a known reference sequence to generate an unbiased early power estimate and for correlating the reference samples from the late despread signal with the known reference sequence to generate an unbiased late power estimate;

(e) difference means for calculating the power difference between the unbiased early power estimate and the unbiased late power estimate; and

(f) delay lock loop means for adjusting sampling time of a demodulator based upon the calculated power difference.

9. The synchronization device of claim 8 wherein the correlating means comprises means for filtering a correlator output and estimating power from the filtered correlator output to generate the unbiased early power estimate and the unbiased late power estimate, and wherein the delay lock loop means comprises means for adjusting sampling time of the demodulator based upon an average of several of said calculated power differences.

10. The synchronization device of claim 8 wherein the extractor further comprises:

(a) extracting means for extracting only reference samples from the early and the late despread signal and for extracting only data samples from the early and the late despread signal;

(b) correlating means for correlating the reference samples from the early despread signal with a known reference sequence to generate an unbiased early power estimate and for correlating the reference samples from the late despread signal with the known reference sequence to generate an unbiased late power estimate;

(c) complex power estimating means for calculating a noisy complex early power estimate from the data samples from the early despread signal and for calculating a noisy complex late power estimate from the data samples from the late despread signal;

(d) averaging means for averaging the noisy complex early power estimate and the noisy complex late power estimate, respectively;

(e) power estimating means for calculating an early data power estimate and a late power estimate from the average noisy complex early data power estimate and the average noisy complex late power estimate, respectively;

(f) combining means for weighting and summing the unbiased early power estimate and the early data power estimate to generate a combined early power estimate and for weighting and summing the unbiased late power estimate and the late data power estimate to generate a combined late power estimate;

(g) difference means for calculating the power difference between the combined early power estimate and the combined late power estimate; and

(h) delay lock loop means for adjusting sampling time of the demodulator based upon the calculated power difference.

11. The synchronization device of claim 10 wherein the delay lock loop means comprises means for adjusting sampling time of the demodulator based upon an average of several of said calculated power differences.

12. A method for coherent reception of spread spectrum communications in a receiver, comprising the steps of:

(a) digitizing a received spread spectrum signal in a sampler and despreading the received spread spectrum signal in a despreader coupled to the sampler into a data signal;

(b) extracting reference sample information from the data signal in an extractor;

(c) adjusting the timing of the received spread spectrum signal based on at least one of the data signal and the reference sample information; and

(d) adjusting one of the group consisting of the phase and frequency of the received spread spectrum signal based on at least one of the data signal and the reference sample information.

13. The method of claim 12, wherein step (c) further comprises determining a first power estimate based on at least one of the data signal and the reference sample information, and adjusting the timing of the received spread spectrum signal based on the power estimate.

14. The method of claim 13, further comprising:

(d) despreading a late replica of the received spread spectrum signal in a further despreader coupled to the sampler into a late replica data signal, extracting late replica reference sample information from the late replica data signal in an extractor, and determining a second power estimate based on at least one of the late replica data signal and the late replica reference sample information; and

(e) adjusting the timing of the received spread spectrum signal based on the first and second power estimates by at least one of adjusting an output timing of the sampler, and controlling a gate coupling one of the data signal and late replica data signal to a coherent detector.

15. The method of claim 14, wherein the sampler comprises a buffer following an analog to digital converter, and the step of adjusting an output timing of the sampler further comprises calculating a power difference between the first and second power estimates and adjusting an output timing of the received spread spectrum signal and the late replica of the received spread spectrum signal from the buffer based on the calculated power difference.

16. The method of claim 14, wherein the step of controlling the gate further comprises determining a greatest one of the first and second power estimates and controlling the gate to connect a one of the data signal and the late replica data signal corresponding with a greatest one of the first and second power estimates, to a coherent detector.