Device for controlling memory data path in parallel processing computer system
First Claim
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1. In a processing node connected to an interconnection network for a parallel processing computer system, a memory data path controller comprising:
- a network queue for temporarily storing memory access data received/transmitted via a network interface;
a bus queue for temporarily storing memory access data received/transmitted via a bus interface of a bus connected to a plurality of processors of said processing node; and
dual path controller means for recognizing memory access requests generated from both said network interface and said bus interface to thereby dually control memory access data reception/transmission between said network queue and said network interface and between said bus queue and bus interface, said means further arbitrating said memory access requests of said network queue and bus queue,whereby a single port memory of said processing node connected to the interconnection the network of said parallel processing computer system is controlled as a dual port.
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Abstract
A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.
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Citations
7 Claims
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1. In a processing node connected to an interconnection network for a parallel processing computer system, a memory data path controller comprising:
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a network queue for temporarily storing memory access data received/transmitted via a network interface; a bus queue for temporarily storing memory access data received/transmitted via a bus interface of a bus connected to a plurality of processors of said processing node; and dual path controller means for recognizing memory access requests generated from both said network interface and said bus interface to thereby dually control memory access data reception/transmission between said network queue and said network interface and between said bus queue and bus interface, said means further arbitrating said memory access requests of said network queue and bus queue, whereby a single port memory of said processing node connected to the interconnection the network of said parallel processing computer system is controlled as a dual port. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification