Device for controlling memory data path in parallel processing computer system

• US 5,659,687 A
• Filed: 04/18/1996
• Issued: 08/19/1997
• Est. Priority Date: 11/30/1995
• Status: Expired due to Term

• Current Assignee: Uniloc 2017 LLC (FIG LLC (d/b/a Fortress Investment Group LLC)), Loral Fairchild Corp. (Newell Brands Inc.)
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: Yoon, Suk-Han, Kim, Seong-Woon, Won, Chul-Ho
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/634,635
• Time in Patent Office: 488 Days
• Field of Search: 395/292, 395/200.2, 395/728, 395/800, 395/200.07, 395/200.03, 395/200.14, 395/474, 395/250
• US Class Current: 710/112
• CPC Class Codes: G06F 13/1642 with request queuing

Abstract

A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.

Claims

1. In a processing node connected to an interconnection network for a parallel processing computer system, a memory data path controller comprising:

a network queue for temporarily storing memory access data received/transmitted via a network interface;

a bus queue for temporarily storing memory access data received/transmitted via a bus interface of a bus connected to a plurality of processors of said processing node; and

dual path controller means for recognizing memory access requests generated from both said network interface and said bus interface to thereby dually control memory access data reception/transmission between said network queue and said network interface and between said bus queue and bus interface, said means further arbitrating said memory access requests of said network queue and bus queue,

whereby a single port memory of said processing node connected to the interconnection the network of said parallel processing computer system is controlled as a dual port.

2. A memory data path controller for a parallel processing computer system as claimed in claim 1, wherein said network queue comprises:

a network reading address queue for sequentially storing reading addresses input via said network interface and for storing an access sequence value of said reading addresses;

a network reading data queue for sequentially storing said memory access data read based on a sequence of said access sequence value and access address stored in said network reading address queue, said queue transmitting said stored memory access data to the network requesting memory access via said network interface;

a network writing address queue for sequentially storing writing addresses input via said network interface and for storing an access sequence value of said writing addresses; and

a network writing data queue for sequentially storing writing data input via said network interface and for writing said stored writing data in said memory according to the sequence of said access sequence values of said reading addresses and said writing addresses.

3. A memory data path controller for a parallel processing computer system as claimed in claim 2, wherein said network reading address queue, network writing address queue, network reading data queue, and network writing data queue all are multi-staged.

4. A memory data path controller for a parallel processing computer system as claimed in claim 1, wherein said bus queue comprises:

a bus reading address queue for sequentially storing reading addresses input via said bus interface and for storing access sequence values of said reading addresses;

a bus reading data queue for sequentially storing said memory access data read based on a sequence of said access sequence values stored in said bus reading address queue, said queue transmitting said stored memory access data to the processor requesting memory access via said bus interface;

a bus writing address queue for sequentially storing writing addresses input via said bus interface and for storing access sequence values of said writing addresses; and

a bus writing data queue for sequentially storing writing data input via said bus interface and for writing said stored writing data in said memory according to a sequence of said access sequence values stored in said bus writing address queue.

5. A memory data path controller for a parallel processing computer system as claimed in claim 4, wherein said bus reading address queue, bus writing address queue, bus reading data queue, and bus writing data queue all are multi-staged, equal to or greater than the number of processors capable of requesting memory access via said bus interface.

6. A memory data path controller for a parallel processing computer system as claimed in claim 1, wherein said dual path controller means comprises:

a queue counter for detecting whether or not said network queue or bus queue is full;

a queue controller for recognizing a memory access request input via said network interface or bus interface and, only if said queue counter is not full, for controlling to perform data transmission/reception between said network queue and network interface and between said bus queue and bus interface;

an access sequencer for providing a sequence of memory accesses between said network queue and bus queue based on a sequence of memory access requests; and

a queue arbiter for accepting an arbitration request from said queue controller and for arbitrating so that said network queue or bus queue accesses said memory and reads or writes data according to priority of the access sequence of said access sequencer.

7. A memory data path controller for a parallel processing computer system as claimed in claim 6, wherein for said network queue'"'"'s reading and writing, two queues are allocated, and for said bus queue'"'"'s writing and reading, two queues are allocated so that a remaining number capable of the respective reading/writing accesses is counted.