Programmably configurable host adapter integrated circuit including a RISC processor

• US 5,659,690 A
• Filed: 10/15/1992
• Issued: 08/19/1997
• Est. Priority Date: 10/15/1992
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: von Stamwitz, Paul, Makishima, Douglas K., Gates, Stillman F., Borkar, Paresh M., Young, Byron Arlen, Stuber, Craig A.
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US07/964,532
• Time in Patent Office: 1,769 Days
• Field of Search: 395/325, 395/800, 395/250, 395/309, 395/306
• US Class Current: 710/307
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

The host adapter integrated circuit is a one chip high performance bus master host adapter for (i) connecting a first bus having a specified protocol for transferring information over the first bus and a first data transfer speed to a second bus having a specified protocol for transferring information over the second bus and a second data transfer speed, and (ii) transferring information between the two buses. The host adapter integrated circuit, hereinafter host adapter, includes a novel reduced instruction set computing (RISC) processor, a first interface module circuit connectable to the first bus and coupled to the RISC processor, a second interface module circuit connectable to the second bus and coupled to the RISC processor, and a memory circuit means connected to the first interface module circuit and to the second interface module circuit and coupled to the RISC processor. An I/O bus interconnects the first interface module circuit, the second interface module circuit, the memory circuit means, and the RISC processor. The I/O bus supports a read and a write operation by the RISC processor in single clock cycle of the RISC processor. The host adapter supports many features found in traditional add-in card SCSI host adapters. These features include bus master transfers, fast/wide SCSI, one interrupt per command, scatter/gather, overlapped seeks, tagged queuing, etc.

Claims

1. A host adapter integrated circuit comprising:

a reduced instruction set computing processor, hereinafter said RISC processor

a first bus interface module circuit connectable to a first bus external to said host adapter integrated circuit, and coupled to said RISC processor;

wherein said first bus interface module circuit transfers information to and from said first bus in response to instructions from said RISC processor; and

said first bus is an I/O bus for at least one peripheral device; and

a second bus interface module circuit connectable to a host computer bus, and coupled to said RISC processor;

wherein said second bus interface module circuit transfers information to and from said host computer bus in response to instructions from said RISC processor;

said RISC processor, said first bus interface module circuit and said second bus interface module circuit are included in said host adapter integrated circuit; and

said first bus interface module circuit transfer of said information to and from said I/O bus for at least one peripheral device, and said second bus interface module circuit transfer of said information to and from said host computer bus are performed in response to bus master host adapter functions performed by said host adapter integrated circuit.

2. The host adapter integrated circuit of claim 1 wherein said second bus interface module circuit is a programmable host computer bus interface module circuit wherein said programmable host computer bus interface module circuit is programmably configurable to interface with any one of a plurality of host computer bus architectures.

3. The host adapter integrated circuit of claim 2 wherein said plurality of host computer bus architectures includes an ISA computer bus architecture and an EISA computer bus architecture.

4. The host adapter integrated circuit of claim 1 further comprising:

a memory circuit connected to said first bus interface module circuit and to said second bus interface module circuit, and coupled to said RISC processor, wherein said memory circuit buffers data so as to keep information streaming from said first bus to said host computer bus during an information transfer between said first bus and said host computer bus.

5. The host adapter integrated circuit of claim 4 further comprising:

a bus connected to said RISC processor, said first bus interface module circuit, said second bus interface module circuit, and said memory circuit

wherein a first portion of said bus is a source bus and a second portion of said bus is a destination bus; and

said bus supports both a read operation and a write operation in one clock cycle of said RISC processor.

6. The host adapter integrated circuit of claim 5 wherein said source bus includes an address bus and a data bus.

7. The host adapter integrated circuit of claim 6 wherein said destination bus includes an address bus and a data bus.

8. The host adapter integrated circuit of claim 4 wherein said memory circuit includes a first-in first-out memory, hereinafter said FIFO memory.

9. The host adapter integrated circuit of claim 8 wherein said FIFO memory has a width equal to a width of said host computer bus.

10. The host adapter integrated circuit of claim 9 wherein said width is 32-bits.

11. The host adapter integrated circuit of claim 8 wherein said second bus interface module further comprises a byte alignment circuit connected to said FIFO memory wherein said byte alignment circuit configures data in any one of a plurality of sizes for transfer through said FIFO memory.

12. The host adapter integrated circuit of claim 11 wherein said plurality of sizes includes a byte, a word, and a double word.

13. The host adapter integrated circuit of claim 11 wherein said byte alignment circuit automatically configures data of a particular size for transfer through said FIFO memory without intervention by said RISC processor.

14. The host adapter integrated circuit of claim 1 wherein said RISC processor includes a pause logic circuit wherein upon receiving a selected input signal, said pause logic circuit generates a signal which pauses operation of said RISC processor.

15. The host adapter integrated circuit of claim 1 further comprising a memory array operatively connected to said RISC processor wherein control blocks for said RISC processor are stored in said memory array;

each of said control blocks has an address; and

each of said control blocks includes a command that is executed by said RISC processor.

16. The host adapter integrated circuit of claim 15 wherein said second bus interface module circuit further comprises a queue-in first-in first out memory, herein after queue-in FIFO, wherein the address for each control block awaiting execution in said memory array is stored in said queue-in FIFO.

17. The host adapter integrated circuit of claim 16 wherein said second bus interface module circuit further comprises a queue-in FIFO counter operatively connected to said queue-in FIFO wherein upon loading or removing an address from said queue-in FIFO, the value of said queue-in FIFO counter is changed.

18. The host adapter integrated circuit of claim 17 wherein said second bus interface module circuit further comprises a control block address pointer register operatively connected to said queue-in FIFO and to said RISC processor wherein to execute the command in a control block, the address of the control block is transferred from said queue-in FIFO to said control block address pointer register.

19. The host adapter integrated circuit of claim 15 wherein said second bus interface module circuit further comprises a queue-out first-in first out memory, herein after said queue-out FIFO, wherein the address for each executed control block in said memory array is stored in said queue-out FIFO.

20. The host adapter integrated circuit of claim 19 wherein said second bus interface module circuit further comprises a queue-out FIFO counter operatively connected to said queue-out FIFO wherein upon loading or removing an address from said queue-out FIFO, the value of said queue-out FIFO counter is changed.

21. The host adapter integrated circuit of claim 1 wherein said second bus interface module circuit includes a register set wherein said register set includes registers having status, control, and configuration bits.

22. The host adapter integrated circuit of claim 1 wherein said first bus is a SCSI bus.

23. The host adapter integrated circuit of claim 22 wherein said first bus interface module circuit is a programmable SCSI bus interface module circuit, wherein said programmable SCSI bus interface module circuit is programmably configurable to drive and, receive information from one of a SCSI bus of a first width and a SCSI bus of a second width and further wherein as first width is different from said second width.

24. The host adapter integrated circuit of claim 23 wherein said SCSI bus interface module circuit is programmably configurable to drive and receive information from a SCSI differential bus.

25. The host adapter integrated circuit of claim 24 wherein said SCSI differential bus has said first width.

26. The host adapter integrated circuit of claim 24 wherein said SCSI differential bus has said second width.

27. The host adapter integrated circuit of claim 22 wherein said first bus interface module circuit is a programmable SCSI bus interface module circuit, wherein said programmable SCSI bus interface module circuit is programmably configurable to drive and receive information from two SCSI buses of the same width.

28. The host adapter integrated circuit of claim 22 wherein said first bus interface module circuit is a programmable SCSI bus interface module circuit, and further wherein said programmable SCSI bus interface module circuit is programmably configurable to drive and receive information from a SCSI differential bus and a single-ended SCSI bus.

29. The host adapter integrated circuit of claim 1 wherein said first bus interface module circuit includes a register set wherein said register set includes registers having status, control, and configuration bits.

30. The host adapter integrated circuit of claim 1 further comprising a register set wherein said register set includes registers having status and control bits for said RISC processor.

31. The host adapter integrated circuit of claim 30 wherein said RISC processor includes an ALU operatively connected to said register set.

32. The host adapter integrated circuit of claim 31 further comprising a RISC processor memory wherein said RISC processor memory includes stored command lines to control processes performed by said RISC processor.

33. The host adapter integrated circuit of claim 32 wherein at least one of said stored command line includes an ALU operation field.

34. The host adapter integrated circuit of claim 32 wherein at least one of said stored command line includes a source address field.

35. The host adapter integrated circuit of claim 32 wherein at least one of said stored command line includes a destination address field.

36. The host adapter integrated circuit of claim 32 wherein each of said stored command lines has a 29 bit width.

37. The host adapter integrated circuit of claim 32 wherein said RISC processor includes a register connected to said RISC processor memory wherein a command line is loaded into said register from said RISC processor memory.

38. The host adapter integrated circuit of claim 32 wherein said RISC processor further comprises a source address circuit.

39. The host adapter integrated circuit of claim 32 wherein said RISC processor further comprises a destination address circuit.

40. In a host computer having a memory, a host computer bus, and a SCSI bus, a host adapter system comprising:

a host adapter integrated circuit, connectable to said host computer bus and to said SCSI bus, including;

a reduced instruction set computing processor, hereinafter said RISC processor;

a SCSI module connectable to said SCSI bus, and coupled to said RISC processor wherein said SCSI module transfers information to and from said SCSI bus in response to instructions from said RISC processor; and

a host interface module connectable to said host computer bus, and coupled to said RISC processor wherein said host interface module transfers information to and from said host computer bus in response to instructions from said RISC processor; and

a host adapter driver, operative in said host computer, for controlling operation of said host adapter integrated circuit wherein said host adapter driver communicates with said host adapter integrated circuit over said host computer bus.

41. The host adapter system of claim 40 wherein said host adapter integrated circuit further comprises:

a memory circuit connected to said SCSI module and to said host interface module, and coupled to said RISC processor, wherein said memory circuit buffers data so as to keep information streaming from SCSI bus to said host computer bus during an information transfer between said SCSI bus and said host computer bus.

42. The host adapter system of claim 41 wherein said host adapter integrated circuit further comprises:

a bus connected to said RISC processor, said SCSI module, said host interface module, and said memory circuit wherein a first portion of said bus is a source bus and a second portion of said bus is a destination bus; and

said bus supports a read operation and a write operation in one clock cycle of said RISC processor.

43. The host adapter system of claim 42 wherein said source bus includes an address bus and a data bus.

44. The host adapter system of claim 42 wherein said destination bus includes an address bus and a data bus.

45. The host adapter system of claim 41 wherein said memory circuit includes a first-in first-out memory, hereinafter said FIFO memory.

46. The host adapter system of claim 45 wherein said FIFO memory has a width equal to a width of said host computer bus.

47. The host adapter system of claim 46 wherein said width is 32-bits.

48. The host adapter system of claim 45 wherein said memory circuit further comprises a byte alignment circuit connected to said FIFO memory wherein said byte alignment circuit configures data in any one of a plurality of sizes for transfer through said FIFO memory.

49. The host adapter system of claim 48 wherein said plurality of sizes includes a byte, a word, and a double word.

50. The host adapter system of claim 48 wherein said byte alignment circuit automatically configures data of a particular size for transfer through said FIFO memory without intervention by said RISC processor.

51. The host adapter system of claim 40 wherein host interface module is a programmable host computer bus interface module and further wherein said programmable host computer bus interface module is programmably configurable to interface with any one of a plurality of host computer bus architectures.

52. The host adapter system of claim 51 wherein said plurality of host computer bus architectures includes an ISA computer bus architecture and an EISA computer bus architecture.

53. The host adapter system of claim 40 wherein said host interface module includes a register set wherein said register set includes registers having status, control, and configuration bits.

54. The host adapter system of claim 40 wherein said SCSI module comprises a programmable SCSI module and further wherein said programmable SCSI module is programmably configurable to drive and receive information from one of a SCSI bus of a first width and a SCSI bus of a second width where said first width is different from said second width.

55. The host adapter system of claim 40 wherein said SCSI module is a programmable SCSI module and further wherein said programmable SCSI module is programmably configurable to drive and receive information from two SCSI buses of the same width.

56. The host adapter system of claim 40 wherein said SCSI module is a programmable SCSI module and further wherein said programmable SCSI module is programmably configurable to drive and receive information from a differential SCSI bus.

57. The host adapter system of claim 56 wherein said differential SCSI bus has a first width.

58. The host adapter system of claim 57 wherein said differential SCSI bus has a second width wherein said second width is different from said first width.

59. The host adapter system of claim 40 wherein said SCSI module is a programmable SCSI module and further wherein said programmable SCSI module is programmably configurable to drive and receive information from a differential SCSI bus and a single-ended SCSI bus.

60. The host adapter system of claim 40 wherein said SCSI module includes a register set and further wherein said register set includes registers having status, control, and configuration bits.

61. The host adapter system of claim 40 further comprising a register set wherein said register set includes registers having status, and control bits for said RISC processor.

62. The host adapter system of claim 61 wherein said RISC processor includes an ALU operatively connected to said register set.

63. The host adapter system of claim 62 further comprising a RISC processor memory wherein said RISC processor memory includes stored command lines to control processes performed by said RISC processor.

64. The host adapter system of claim 63 wherein at least one of said stored command lines includes an ALU operation field.

65. The host adapter system of claim 63 wherein at least one of said stored command lines includes a source address field.

66. The host adapter system of claim 63 wherein at least one of said stored command lines includes a destination address field.

67. The host adapter system of claim 63 wherein each of said stored command lines has a 29-bit width.

68. The host adapter system of claim 63 wherein said RISC processor includes a register connected to said RISC processor memory wherein a command line is loaded into said register from said RISC processor memory.

69. The host adapter system of claim 63 wherein said RISC processor further comprises a source address circuit.

70. The host adapter system of claim 63 wherein said RISC processor further comprises a destination address circuit.

71. The host adapter system of claim 40 wherein said host adapter integrated circuit further comprises a memory array operatively connected to said RISC processor wherein control blocks for said RISC processor are stored in said memory array;

each of said control blocks has an address; and

each of said control blocks includes a command that is executed by said RISC processor.

72. The host adapter system of claim 71 wherein said host interface module further comprises a queue-in first-in first out memory, herein after queue-in FIFO, wherein the address for each control block awaiting execution in said memory array is stored in said queue-in FIFO.

73. The host adapter system of claim 72 wherein said host interface module further comprises a queue-in FIFO counter operatively connected to said queue-in FIFO wherein upon loading or removing an address from said queue-in FIFO, the value of said queue-in FIFO counter is changed.

74. The host adapter system of claim 73 wherein said host interface module further comprises a control block address pointer register operatively connected to said queue-in FIFO and to said RISC processor wherein to execute the command in a control block, the address of the control block is transferred from said queue-in FIFO to said control block address pointer register.

75. The host adapter integrated system claim 74 wherein said host interface module further comprises a queue-out first-in first out memory, hereinafter said queue-out FIFO, wherein the address for each executed control block in said memory array is stored in said queue-out FIFO.

76. The host adapter system of claim 75 wherein said host interface module further comprises a queue-out FIFO counter operatively connected to said queue-out FIFO wherein upon loading or removing an address from said queue-out FIFO, the value of said queue-out FIFO counter is changed.

77. The host adapter system of claim 71 wherein said host adapter driver means further comprises means, operatively coupled to said queue-in FIFO and said memory array, for sending a control block to said memory array.

78. The host adapter system of claim 77 wherein said sending means further comprises means for determining the fullness of said memory array wherein upon detection of said memory array being full, said determining means queues said control block in said host computer memory.

79. The host adapter system of claim 78 wherein said RISC processor includes a pause logic circuit having a plurality of input lines wherein upon receiving an input signal on any one of said plurality of input lines, said pause logic circuit generates a signal which pauses operation of said RISC processor.

80. The host adapter system of claim 79 wherein said sending means further comprises means, operatively coupled to said pause logic circuit, for generating a signal to an input line of said pause logic circuit wherein prior to said sending means sending a control block to said memory array, said signal generating means sends a signal to said pause logic thereby pausing said RISC processor.

81. The host adapter system of claim 80 wherein said sending means further comprises means for placing the address of said control block in said queue-in FIFO.

82. In a host adapter integrated circuit having a RISC processor, a first bus interface module and a second bus interface module, a bus structure comprising:

a source address bus connected to said RISC processor, said first bus interface module, and said second bus interface module;

a source data bus connected to said RISC processor, said first bus interface module, and said second bus interface module;

a destination address bus connected to said RISC processor, said first bus interface module, and said second bus interface module;

a destination data bus connected to said RISC processor, said first bus interface module, and said second bus interface module; and

a plurality of control signal lines;

wherein said bus structure supports a read operation and a write operation in one RISC processor clock cycle;

said first bus interface module transfers data to and from an I/O bus for at least one peripheral device; and

said second bus interface module transfers data to and from a host computer bus within host computer;

said first bus interface module transfers of said information to and from said I/O bus for at least one peripheral device, and said second bus interface module transfers of said information to and from said host computer bus are performed in response to bus master host adapter functions performed by said host adapter integrated circuit using said bus structure.

83. In a host adapter integrated circuit, a sequencer comprising:

a reduced instruction set computing processor, hereinafter said RISC processor, having an address space wherein said RISC processor is included within said host adapter integrated circuit and said address space defines memory addressable by said RISC processor; and

a memory, operatively connected to said RISC processor,

wherein said memory is within the address space of said RISC processor; and

firmware for said RISC processor included in said host adapter integrated circuit is stored in a portion of said memory contained within said host adapter integrated circuit; and

said RISC processor in said host adapter integrated circuit supports operations of said host adapter integrated circuit as a high speed bus master host adapter between a SCSI bus and a host computer bus by executing said firmware.

84. In a host adapter integrated circuit, the sequencer of claim 83 wherein said memory includes a random access memory and a register set.

85. In a host adapter integrated circuit, the sequencer of claim 84 wherein said register set includes registers having status, control, and configuration bits for said RISC processor.

86. In a host adapter integrated circuit, the sequencer of claim 84 wherein said RISC processor includes an ALU, operatively connected to said register set, having first and second input ports and an output port.

87. In a host adapter integrated circuit, the sequencer of claim 84 further comprising random access memory wherein said random access memory includes stored command lines to control processes performed by said RISC processor.

88. In a host adapter integrated circuit, the sequencer of claim 87 wherein at least one of said stored command lines includes an ALU operation field.

89. In a host adapter integrated circuit, the sequencer of claim 87 wherein at least one of said stored command lines includes a source address field.

90. In a host adapter integrated circuit, the sequencer of claim 87 wherein at least one of said stored command lines includes a destination address field.

91. In a host adapter integrated circuit, the sequencer of claim 87 wherein each of said stored command lines has a 29-bit width.

92. In a host adapter integrated circuit, the sequencer of claim 87 wherein said RISC processor includes a register connected to said random access memory wherein a command line is loaded into said register from said random access memory.

93. In a host adapter integrated circuit, the sequencer of claim 83 wherein said RISC processor further comprises a source address circuit.

94. In a host adapter integrated circuit, the sequencer of claim 83 wherein said RISC processor further comprises a destination address circuit.

95. In a host adapter integrated circuit, a programmable SCSI bus interface module comprising:

a first programmable SCSI cell wherein said first programmable SCSI cell is programmably configurable to support one of a differential SCSI bus and a single-ended SCSI bus; and

a second programmable SCSI cell wherein said second programmable SCSI cell supports a single-ended SCSI bus; and

a control module coupled to said first and second programmable SCSI cells;

wherein said first and second programmable SCSI cells are programmably configured by setting and clearing bits in said control module.

96. In a host adapter integrated circuit, the programmable SCSI bus interface module of claim 95 wherein said SCSI bus is a SCSI-3 bus.

97. In a host adapter integrated circuit, the programmable SCSI bus interface module of claim 95 wherein said first and second programmable SCSI cells each include a SCSI first-in-first-out memory for buffering information to and from said SCSI bus.

98. In a host adapter integrated circuit, the programmable SCSI bus interface module of claim 97 wherein said first and second programmable SCSI cells each include a register set wherein registers in said register set include control, configuration, and status information.

99. In a host adapter integrated circuit, the programmable SCSI bus interface module of claim 97 wherein only one of said programmable SCSI cells is active at a time.

100. A host adapter integrated circuit comprising:

host computer bus interface module for connecting to a host computer bus external to said host adapter integrated circuit;

a SCSI bus interface module for connecting to a SCSI bus external to said host adapter integrated circuit; and

a data FIFO memory circuit connected to said host computer bus and SCSI bus interface modules, and having a programmable data threshold

wherein upon the amount of data in said data FIFO memory circuit reaching said programmable data threshold, said data FIFO memory circuit generates a signal to said host computer bus interface module and in response thereto, said host computer bus interface module generates a signal seeking control of said first bus, and further wherein said programmable data threshold is configured to facilitate transfer of said data between said host computer bus and said SCSI bus.