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Programmably configurable host adapter integrated circuit including a RISC processor

  • US 5,659,690 A
  • Filed: 10/15/1992
  • Issued: 08/19/1997
  • Est. Priority Date: 10/15/1992
  • Status: Expired due to Term
First Claim
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1. A host adapter integrated circuit comprising:

  • a reduced instruction set computing processor, hereinafter said RISC processora first bus interface module circuit connectable to a first bus external to said host adapter integrated circuit, and coupled to said RISC processor;

    wherein said first bus interface module circuit transfers information to and from said first bus in response to instructions from said RISC processor; and

    said first bus is an I/O bus for at least one peripheral device; and

    a second bus interface module circuit connectable to a host computer bus, and coupled to said RISC processor;

    wherein said second bus interface module circuit transfers information to and from said host computer bus in response to instructions from said RISC processor;

    said RISC processor, said first bus interface module circuit and said second bus interface module circuit are included in said host adapter integrated circuit; and

    said first bus interface module circuit transfer of said information to and from said I/O bus for at least one peripheral device, and said second bus interface module circuit transfer of said information to and from said host computer bus are performed in response to bus master host adapter functions performed by said host adapter integrated circuit.

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