Multiport memory and method of arbitrating an access conflict therein

• US 5,659,711 A
• Filed: 08/31/1994
• Issued: 08/19/1997
• Est. Priority Date: 03/13/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sugita, Mitsuru
• Primary Examiner(s): Elmore, Reba I.
• Application Number:
  US08/298,082
• Time in Patent Office: 1,084 Days
• Field of Search: 395/458, 395/476, 395/477, 395/495
• US Class Current: 711/144
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

A multiport memory includes a first memory block and a second memory block which are independently accessible with each other. Each of the first and second memory blocks can be accessed simultaneously through first and second ports. The memory includes a first access conflict detector for detecting an access conflict on the first memory block, a second access conflict detector for detecting an access conflict in the second memory block, a first arbitor responsive to the first detector for arbitrating an access conflict in the first memory block, and a second arbitor responsive to the second detector for arbitrating an access conflict in the second memory block. The memory further includes a selector for transferring the arbitration result of the first arbitor to the second memory block while neglecting the arbitration result of the second arbitor only when both the first and second detector detect the access confliction.

Claims

1. A multiport memory including a first port and a second port which can be accessed independently from each other, comprising:

a plurality of memory blocks each having an array of memory cells, each said memory block being accessible through said first and second ports, each of said first and second ports including a plurality of subports corresponding to said plurality of memory blocks;

a plurality of access conflict detecting means, one for each said memory block, each for determining whether or not an access through a subport of said first port to a corresponding memory block conflicts with an access through a subport of said second port to the corresponding memory block in response to address signals for the first and second ports;

a plurality of arbitrating means provided corresponding to each respective access conflict detecting means and responsive to an associated access conflict detecting means for effecting an arbitration for avoiding an access confliction to generate an enabling signal for allowing an access to a preferential port;

selection means responsive to said plurality of access conflict detecting means for selectively passing the enabling signal from one of said plurality of arbitrating means; and

,

port control means provided for each respective memory block and responsive to said selection means for enabling an access to a port enabled by the enabling signal received from said selection means, said selection means responsive to a multiple of the access conflict detecting means simultaneously detecting access conflictions in corresponding memory blocks, for selecting and passing an enabling signal from one of arbitration means corresponding to the multiple of the access conflict detecting means to each respective port control means provided corresponding to memory blocks subject to the simultaneous access conflictions.

2. A multiport memory according to claim 1, wherein said selection means includes determination means responsive to said plurality of access conflict detecting means for determining whether or not all of said access conflict detecting means detect an access confliction, and gate means responsive to said determination means for passing the output of only one of said plurality of arbitrating means to each said port control means when said determination means determines that all of said access conflict detecting means detect the access confliction.

3. A multiport memory according to claim 1, wherein said memory blocks include a first memory block and a second memory block and wherein said selection means includes (a) determination means responsive to two access conflict detecting means provided for said first and second memory blocks, for determining whether or not both said two access conflict detecting means detect an access confliction, (b) a first transfer means for transferring the enabling signal from the arbitrating means for the first memory block to the port control means for the first memory block, and (c) a second transfer means responsive to said determination means for selectively passing one of the enabling signals from the arbitrating means for the first memory block and the arbitrating means for the second memory means to the port control means for the second memory block.

4. A multiport memory according to claim 3, wherein said second transfer means transfer the enabling signal from the arbitrating means when said determination means indicates that both said associated two access conflict detecting means detect the access confliction.

5. A multiport memory according to claim 3, wherein the number of said memory blocks is 2, and one memory block provides a high order byte data storage, and the other memory block provides a low order byte data storage.

6. A multiport memory according to 3, wherein said first and second memory blocks are integrated on the same semiconductor chip.

7. A multiport memory according to claim 3, wherein one of said first and second memory blocks provides a high order byte data storage, and the other provides a low order byte data storage.

8. A multiport memory according to claim 3, wherein said first and second memory blocks are formed on separate first and second semiconductor chips respectively, and wherein said first semiconductor memory chip includes an additional determining means receiving an output of the access conflict detecting means for the first memory block and fixed to a disable state, and gating means as said first transfer means responsive to said additional determining means, whereby said first and second semiconductor chips have the same component arrangement with each other.

9. A method of avoiding an access confliction in a multiport memory having independently accessible first and second ports, said multiport memory including a first memory block and a second memory block, said method comprising the steps of:

independently determining whether or not there is an access confliction between an access through said first port and an access through said second port in said first memory block and in said second memory block;

carrying out an arbitration operation on an access to a memory block causing an access confliction to allow an access through one of said first and second ports while allowing accesses through the first and second ports of a memory block causing no access confliction, when only one of the first and second memory blocks is subject to the access confliction, and

carrying out an arbitration operation on accesses to both the first and second memory blocks to allow an access to the first and second memory blocks through one of said first and second ports determined by the arbitration operation carried out for one of the first and second memory blocks, when both the first and second memory blocks are subject to the access confliction.