Method for forming and tailoring the electrical characteristics of semiconductor devices

• US 5,661,045 A
• Filed: 12/09/1996
• Issued: 08/26/1997
• Est. Priority Date: 05/24/1993
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lowrey, Tyler, Rhodes, Howard, Dennison, Charles, Manning, Monte
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): MULPURI, SAVITRI
• Application Number:
  US08/763,848
• Time in Patent Office: 260 Days
• Field of Search: 437/40 AS, 437/41 AS, 437/45, 437/52, 437/69, 437/29, 437/913, 437/57, 437/34, 437/933, 437/56
• US Class Current: 438/286
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

A method for forming semiconductor devices includes a low energy implant for tailoring the electrical characteristics of the semiconductor devices. Using the low energy implant, narrow width devices such as access transistors in an SRAM cell, can be fabricated with a low threshold voltage (Vt). The low energy implant is performed on the active areas of a silicon substrate following field isolation and field implant. For an n-conductivity access transistor, the low energy dopant can be an n-type dopant such as phosphorus, arsenic or antimony.

Claims

1. A method for fabricating semiconductor devices, comprising:

providing a substrate;

forming active areas on the substrate;

isolating the active areas with a field oxide;

forming a mask on the substrate having openings therein for exposing selected active areas while protecting remaining active areas;

implanting a dopant with sufficient energy such that the dopant penetrates through the field oxide and into the substrate for defining isolation field areas on the substrate and the dopant penetrates into the selected active areas;

implanting a second dopant through the openings into the selected active areas, said second dopant comprising a different conductivity type than said dopant in order to lower a threshold voltage of a transistor to be formed in the selected active areas; and

continuing processing to form active semiconductor devices in the active areas.

2. The method as recited in claim 1 and wherein the dopant is a p-conductivity type dopant and the second dopant is an n-conductivity type dopant.

3. The method as recited in claim 1 and wherein the dopant is an n-conductivity type dopant and the second dopant is a p-conductivity type dopant.

4. The method as recited in claim 1 and wherein the dopant is boron and the second dopant is selected from the class consisting of phosphorus, arsenic and antimony.

5. A method of fabricating semiconductor devices, comprising;

providing a substrate;

forming active areas on the substrate;

isolating the active areas using a local oxidation of silicon process to form a field oxide between the active areas;

forming a mask on the substrate having openings therein for exposing selected active areas and the field oxide while covering remaining active areas;

performing a field implant by implanting a p-type conductivity dopant through the field oxide and into the substrate for defining isolation field areas on the substrate and through the openings into the selected active areas;

implanting an n-type conductivity dopant through the openings into the selected active areas to lower a threshold voltage for devices to be formed in the selected active areas; and

continuing processing of the substrate to form active semiconductor devices in the active areas.

6. The method as recited in claim 5 and wherein the semiconductor devices include static random access memories and the selected active areas have a width of less than 1 μ

m.

7. The method as recited in claim 5 and wherein the semiconductor devices include dynamic random access memories and the selected active areas have a width of less than 1 μ

m.

8. The method as recited in claim 5 and wherein the selected active areas include different regions of an active semiconductor device.

9. A method of fabricating semiconductor devices, comprising;

providing a substrate;

forming active areas on the substrate;

forming a field oxide between the active areas using a local oxidation of silicon process;

forming a mask having openings therein for exposing selected active areas and the field oxide while covering remaining active areas;

performing a field implant by implanting a dopant through the field oxide and into the substrate for defining isolation field areas on the substrate and through the openings into the selected active areas;

lowering a threshold voltage for devices to be formed in the selected active areas, said devices having a width less than 1 μ

m, by implanting a second dopant having a different conductivity type than the dopant through the openings into the selected active areas; and

forming active semiconductor devices in the active areas.

10. The method as recited in claim 9 and wherein the dopant is a p-conductivity type dopant and the second dopant is an n-conductivity type dopant.

11. The method as recited in claim 10 and wherein the dopant is an n-conductivity type dopant and the second dopant is a p-conductivity type dopant.