Method of making dense flash EEPROM cell array and peripheral supporting circuits formed in deposited field oxide with the use of spacers

• US 5,661,053 A
• Filed: 05/25/1994
• Issued: 08/26/1997
• Est. Priority Date: 05/25/1994
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Yuan, Jack H.
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/248,735
• Time in Patent Office: 1,189 Days
• Field of Search: 437/40, 437/41, 437/43, 437/44, 437/48, 437/52, 437/240
• US Class Current: 438/257
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor
• CPC Class Codes: H10B 41/48 with a tunnel dielectric layer also being used as part of the peripheral transistor
• CPC Class Codes: Y10S 438/917 Deep level dopants, e.g. gold, chromium, iron or nickel
• CPC Class Codes: Y10S 438/947 Subphotolithographic processing

Abstract

Techniques of forming a flash EEPROM cell array with the size of individual cells being reduced, thereby increasing the number of cells which may be formed on a semiconductor substrate of a given size. Use of dielectric spacers in several steps of the process controls areas being etched or implanted with ions to something smaller than can be obtained by the highest resolution photolithography. Both split-channel and non-split-channel (no select transistor) types of memory cells are included. Example cells employ three polysilicon layers, having separate floating, control and erase gates. A technique of forming the memory cell gates with greater uniformity of conductivity level includes depositing undoped polysilicon and then using ion implantation to introduce the dopant. Field oxide is formed at an early stage in the process by CVD deposition and dry etching. The memory cell array and adjacent peripheral components are formed in a coordinated manner on a single integrated circuit chip.

Claims

1. A method of implanting ions into a surface of a semiconductor substrate in a pattern thereacross including elongated regions which are spaced apart in a direction orthogonal to their lengths and having channel regions interposed between adjacent elongated regions, comprising the steps of:

forming a mask on said semiconductor substrate surface with apertures therethrough that define said elongated regions through which ions are implanted into the substrate, method of forming said mask including the steps of;

depositing a first layer of dielectric on said substrate with a thickness sufficient to block said ions from passing therethrough,

etching a plurality of openings through said first layer of dielectric in a manner to include said pattern and to form sharp sidewalls having a width therebetween,

depositing a second layer of dielectric on said first dielectric layer and said opening sidewalls, said second layer being deposited to a thickness less than one half of said etched opening width, and

anisotropically etching said second layer in a manner to leave spacers along the opening sidewalls, thereby narrowing the widths of the openings in the first dielectric layer to form said apertures,

directing ions against the first layer of dielectric, spacers and apertures, thereby implanting ions through said apertures into the substrate surface in said pattern, and

forming floating gate electrodes over at least a portion of said channel regions.

2. The method according to claim 1, comprising an additional step, after the ion implanting step, of completely removing said first dielectric layer and said spacers.

3. The method according to claim 2 wherein the removal step includes removing all material from said substrate surface, whereby a circuit structure employing said ion implanted regions may then be formed on the substrate surface.

4. The method according to claim 2 wherein the step of depositing a first dielectric layer includes depositing said first dielectric layer directly on the substrate surface.

5. The method according to claim 1 wherein the steps of depositing the first and second layers of dielectric each include depositing undoped silicon dioxide.

7. The method according to claim 1 wherein the step of depositing the first layer of dielectric includes doing so by a chemical vapor deposition process, and further wherein the step of etching openings through the first dielectric layer includes doing so with a dry etch process.

8. The method according to claim 1 wherein the step of etching the first layer of dielectric includes doing so by forming a photoresist mask on the first dielectric layer that has been patterned by a photolithography process in a manner that makes the width between opposing sidewalls of the openings substantially equal to a resolution limit of said process.

23. The method according to claim 1 further having the step of forming erase gate electrodes over said substrate that is capacitively coupled to said floating gate electrodes.

6. A method of implanting ions into a surface of a semiconductor substrate in a given pattern there across including elongated regions which are spaced apart in a direction orthogonal to their lengths, comprising the steps of:

forming a mask on said semiconductor substrate surface with apertures therethrough that define said elongated regions through which ions are implanted into the substrate, a method of forming said mask including the steps of;

depositing a first layer of dielectric on said substrate with a thickness sufficient to block said ions from passing therethrough,

etching a plurality of openings through said first layer of dielectric in a manner to include said given pattern and to form sharp sidewalls having a given width therebetween,

depositing a second layer of dielectric on said first dielectric layer and said opening sidewalls, said second layer being deposited to a thickness less than one half of said etched opening given width, wherein the steps of depositing the first and second layers of dielectric each include depositing doped silicon dioxide, and

anisotropically etching said second layer in a manner to leave spacers along the opening sidewalls, thereby narrowing the widths of the openings in the first dielectric layer to form said apertures, and

directing ions against the first layer of dielectric, spacers and apertures, thereby implanting ions through said apertures into the substrate surface in said given pattern.

9. A method of implanting a plurality of elongated source and drain regions spaced apart across a surface of a semiconductor substrate in a direction orthogonal to their lengths and having channel regions interposed between adjacent elongated regions comprising the steps of:

(1) forming an ion implant mask on said semiconductor substrate surface with apertures therethrough that define said elongated regions a method of forming said mask including the steps of;

(a) a depositing at least a first slayer of material over said substrate with a thickness sufficient to block said ions from passing therethrough,

(b) a forming, over said at least the first layer of material, an etchant mask with elongated openings at positions of the source and drain regions, said etchant mask being formed by a photolithography process and having openings with widths substantially equal to a smallest element that can be resolved by the photolithography process,

(c) anisotropically etching, through the etchant mask openings, elongated trenches through said at least the first layer of material with sharp sidewalls having widths therebetween substantially equal to said smallest element, and

(d) forming spacers along the sidewalls of said trenches, thereby narrowing the widths of the openings in said at least the first layer of material to form apertures therethrough having widths less than said smallest element, and

(2) directing ions through said apertures and into the substrate surface, thereby implanting said elongated source and drain regions and forming floating gate electrodes over at least a portion of said channel regions.

11. The method according to claim 9, wherein the step of depositing at least, a first layer of material includes depositing a dielectric.

21. The method according to claim 9, wherein the ion implanting step includes directing ions into the substrate surface with a dose within a range of about 1×

10¹⁴ to 2×

10¹⁵ ions per square centimeter.

10. A method of implanting a plurality of elongated source and drain regions spaced apart across a surface of a semiconductor substrate in a direction orthogonal to their lengths, comprising the steps of:

(1) forming a gate oxide layer on said substrate surface,

(2) depositing a first polysilicon layer on said gate oxide layer,

(3) forming an ion implant mask on said first polysilicon layer with apertures therethrough that define said elongated regions, a method of forming said mask including the steps of;

(a) depositing a layer of dielectric material over said polysilicon layer with a thickness sufficient to block said ions from passing therethrough,

(b) forming, over said layer of dielectric material, an etchant mask with elongated openings at positions of the source and drain regions, said etchant mask being formed by a photolithography process and having openings with widths substantially equal to a smallest element that can be resolved by the photolithography process,

(c) anisotropically etching, through the etchant mask openings, elongated trenches through all of the layer of dielectric material, the polysilicon layer, and the gate oxide layer with sharp sidewalls having widths therebetween substantially equal to said smallest element, and

(d) forming spacers along the sidewalls of said trenches, including along sidewalls of the polysilicon layer, thereby narrowing the widths of the openings to form apertures therethrough having widths less than said smallest element, and

(4) directing ions through said apertures and into the substrate surface, thereby implanting said elongated source and drain regions.

22. The method according to claim 10, wherein the ion implanting step includes directing ions into the substrate surface with a dose within a range of about 1×

10¹⁴ to 2×

10¹⁵ ions per square centimeter.

12. A method of forming source and drain regions in a surface of a semiconductor substrate that are self aligned with edges of polysilicon elements, comprising the steps of:

forming undoped dielectric on the substrate surface,

depositing a layer of polysilicon material over the undoped dielectric,

depositing a first doped dielectric layer over said polysilicon layer with a thickness sufficient to block ions from passing therethrough during a subsequent ion implantation step, thereby to protect the polysilicon layer,

dry etching a plurality of openings in a defined pattern through both said first doped dielectric layer and said polysilicon layer in a manner to form the openings with sharp sidewalls substantially perpendicular to said substrate surface and with a defined width therebetween,

depositing a second doped dielectric layer on said first doped dielectric layer and along the sidewalls of said openings, said second layer being deposited to a thickness less than one half of the defined width of said openings,

anisotropically etching said second doped dielectric layer in a manner to leave spacers covering the opening sidewalls of both the first doped dielectric layer and the polysilicon layer, thereby forming apertures that are narrower than the defined width of the openings and protecting the exposed sidewalls of the polysilicon layer from the subsequent ion implantation step,

implanting ions into the surface of the substrate through said apertures, and

removing the first and second doped dielectric layers by an etch that leaves the undoped dielectric in place.

15. The method according to claim 12 wherein the step of etching a plurality of openings includes etching the plurality of openings in elongated shapes having lengths extending in a first direction that is substantially perpendicular to a second direction of their widths.

20. The method according to claim 12 wherein the step of depositing the layer of polysilicon material includes depositing the polysilicon in undoped form at a temperature equal to or greater than about 620 degrees Celsius, followed by an additional step of implanting ions into the deposited polysilicon.

13. A method of forming source and drain regions in a surface of a semiconductor substrate that are self aligned with edges of polysilicon elements comprising the steps of:

depositing a layer of polysilicon material in a manner to be carried by the substrate surface,

depositing a first doped silicon dioxide layer over said polysilicon layer with a thickness sufficient to block ions from passing therethrough during a subsequent ion implantation step, thereby to protect the polysilicon layer,

dry etching a plurality of openings in a defined pattern through both said first doped silicon dioxide layer and said polysilicon layer in a manner to form the openings with sharp sidewalls substantially perpendicular to said substrate surface and with a defined width therebetween,

depositing a second doped silicon dioxide layer on said first doped silicon dioxide layer and along the sidewalls of said openings, said second layer being deposited to a thickness less than one half of the defined width of said openings,

anisotropically etching said second doped silicon dioxide layer in a manner to leave spacers covering the opening sidewalls of both the first doped silicon dioxide layer and the polysilicon layer, thereby forming apertures that are narrower than the defined width of the openings and protecting the exposed sidewalls of the polysilicon layer from the subsequent ion implantation step, and

implanting ions into the surface of the substrate through said aperatures.

14. A method of forming source and drain regions in a surface of a semiconductor substrate that are self aligned with edges of polysilicon elements, comprising the steps of:

depositing a layer of polysilicon material in a manner to be carried by the substrate surface,

depositing a first dielectric layer over said polysilicon layer with a thickness sufficient to block ions from passing therethrough during a subsequent ion implantation step, thereby to protect the polysilicon layer,

dry etching a plurality of openings in a defined pattern through both said first dielectric layer and said polysilicon layer in a manner to form the openings with sharp sidewalls substantially perpendicular to said substrate surface and with a defined width therebetween, wherein the step of etching said plurality of openings includes doing so by forming a photoresist mask on the first dielectric layer that has been patterned by a photolithography process in a manner that makes the defined width between opposing sidewalls of the openings substantially equal to a resolution element of said process,

depositing a second dielectric layer on said first dielectric layer and along the sidewalls of said openings, said second layer being deposited to a thickness less than one half of the defined width of said openings,

anisotropically etching said second dielectric layer in a manner to leave spacers covering the opening sidewalls of both the first dielectric layer and the polysilicon layer, thereby forming apertures that are narrower than the defined width of the openings and protecting the exposed sidewalls of the polysilicon layer from the subsequent ion implantation step, and

implanting ions into the surface of the substrate through said apertures.

16. A method of forming source and drain regions in a surface of a semiconductor substrate that are self aligned with edges of polysilicon elements, comprising the steps of:

forming strips of field oxide elongated in a second direction and spaced apart in a first direction that is substantially perpendicular to the second direction,

depositing a layer of polysilicon material over and in between the field oxide strips,

depositing a first dielectric layer over said polysilicon layer with a thickness sufficient to block ions from passing therethrough during a subsequent ion implantation step, thereby to protect the polysilicon layer,

dry etching a plurality of openings in a defined pattern through both said first dielectric layer and said polysilicon layer in a manner to form the openings with sharp sidewalls substantially perpendicular to said substrate surface and with a defined width therebetween, wherein the step of etching a plurality of openings includes etching the plurality of openings in elongated shapes having lengths extending in the first direction and widths in the second direction and removing portions of the field oxide within said apertures,

depositing a second dielectric layer on said first dielectric layer and along the sidewalls of said openings, said second layer being deposited to a thickness less than one half of the defined width of said openings,

anisotropically etching said second dielectric layer in a manner to leave spacers covering the opening sidewalls of both the first dielectric layer and the polysilicon layer, thereby forming apertures that are narrower than the defined width of the openings and protecting the exposed sidewalls of the polysilicon layer from the subsequent ion implantation step, and

implanting ions into the surface of the substrate through said apertures.

17. The method according to claim 16 wherein the step of forming strips of field oxide includes the steps of depositing a layer of field oxide by a chemical vapor deposition process and removing portions of the field oxide layer by a dry etch process.

18. A method of forming source and drain regions in a surface of a semiconductor substrate that are self aligned with edges of polysilicon elements, comprising the steps of:

forming a layer of field oxide in a manner to be carried by said substrate,

dry etching the field oxide layer in a manner to form elongated field oxide strips having lengths extending in said second direction and sidewalls substantially perpendicular to the substrate surface and spaced apart in said first direction, thereby forming sharp edged trenches,

forming spacers along the sidewalls of the trenches from a third deposited dielectric layer,

growing a gate oxide layer on the substrate surface between said spacers,

depositing a layer of polysilicon material over the field oxide strips, trench spacers and gate oxide,

depositing a first dielectric layer over said polysilicon layer with a thickness sufficient to block ions from passing therethrough during a subsequent ion implantation step, thereby to protect the polysilicon layer,

dry etching a plurality of openings in a defined pattern through both said first dielectric layer and said polysilicon layer in a manner to form the openings with sharp sidewalls substantially perpendicular to said substrate surface and with a defined width of the therebetween, wherein the step of etching a plurality of openings includes etching the plurality of openings in elongated shapes having lengths extending in a first direction that is substantially perpendicular to a second direction of their widths,

depositing a second dielectric layer on said first dielectric layer and along the sidewalls of said openings, said second layer being deposited to a thickness less than one half of the defined width of said openings,

anisotropically etching said second dielectric layer in a manner to leave spacers covering the opening sidewalls of both the first dielectric layer and the polysilicon layer, thereby forming apertures that are narrower than the defined width of the openings and protecting the exposed sidewalls of the polysilicon layer from the subsequent ion implantation step, and

implanting ions into the surface of the substrate through said apertures.

19. The method according to claim 18 wherein the step of etching the field oxide layer includes doing so by forming a photoresist mask on the deposited field oxide layer that has been patterned by a photolithography process in a manner that makes the space between opposing sidewalls of the openings substantially equal to a resolution element of said process.