Power transistor device having ultra deep increased concentration

• US 5,661,314 A
• Filed: 09/30/1994
• Issued: 08/26/1997
• Est. Priority Date: 05/09/1990
• Status: Expired due to Term

• Current Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Original Assignee: International Rectifier Corporation (Infineon Technologies AG)
• Inventors: Gould, Herbert J., Merrill, Perry
• Primary Examiner(s): Monin, Jr., Donald L.
• Application Number:
  US08/316,112
• Time in Patent Office: 1,061 Days
• Field of Search: 257/139, 257/142, 257/144, 257/145, 257/339, 257/342
• US Class Current: 257/144
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7398 with both emitter and collector contacts in the same substrate side
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A cellular insulated gate bipolar transistor ("IGBT") device employs increased concentration in the active region between spaced bases to a depth greater than the depth of the base regions. The implant dose which is the source of the increased concentration is about 3.5×10¹² atoms per centimeter squared and is driven for about 10 hours at 1175° C. Lifetime is reduced by an increased radiation dose to reduce switching loss without reducing breakdown voltage or increasing forward voltage drop above previous levels. The increased concentration region permits a reduction in the spacing between bases and provides a region of low localized bipolar gain, increasing the device latch current. The avalanche energy which the device can successfully absorb while turning off an inductive load is significantly increased. The very deep increased conduction region is formed before the body and source regions in a novel process for making the new junction pattern.

Claims

1. A power transistor device having bipolar device forward current carrying characteristics and MOS gate control characteristics;

said device comprising a thin chip of semiconductor material having a substrate of one conductivity type, a lightly doped layer of semiconductor material of the opposite conductivity type disposed atop one surface of said substrate, a plurality of spaced base regions of said one conductivity type extending into the opposite surface of said layer of semiconductor material to a given depth, a plurality of source regions of said opposite conductivity type formed in respective ones of said plurality of spaced base regions and defining respective surface channel regions, a gate insulation layer disposed over said channel regions, a conductive gate layer disposed over said gate insulation layer, a first main electrode connected to said plurality of source regions and a second main electrode connected to said substrate, the regions between said spaced base regions having an increased concentration of carriers of said opposite conductivity type which extends from said opposite surface to a depth greater than the depth of said base regions;

said increased concentration being greater than that of the remaining portion of said layer of semiconductor material over its full depth.

2. The device of claim 1, wherein said increased conductivity regions are formed by an implant dose of greater than about 3×

10¹² atoms per square centimeter of a dopant of said opposite conductivity type followed by a diffusion for about 10 hours at about 1175°

C.

3. The device of claim 1, wherein said increased conductivity regions have a depth greater than about 6 microns.

4. The device of claim 1, wherein said base regions have a cellular topology.

5. The device of claim 4, wherein said cellular base regions have a hexagonal geometry.

6. The device of claim 1, wherein said base regions have an elongated geometry.

7. The device of claim 1, wherein a further layer of said opposite conductivity type, which is more highly doped than said lightly doped layer and which is thinner than said lightly doped layer, is disposed between said layer and said substrate.

8. The device of claim 1, wherein the space between adjacent bases is less than about 12 microns, thus increasing the latch current of said device while the forward voltage drop is reduced.

9. The device of claim 7, wherein said layer of lightly doped opposite conductivity is fully depleted under blocking voltage conditions.

10. The device of claim 1, wherein the bottom of said regions of increased concentration define a symmetrical pattern deeper than said deep bases and facing said drain electrode, which pattern has the topology of said spaced regions over the surface area of said thin chip to define an enlarged area of preferred avalanche breakdown in said enlarged area and to increase the I² L capability of said device.

11. The device of claim 1, wherein the lifetime of said chip is reduced.

12. The device of claim 11, wherein said chip is irradiated to reduce lifetime;

said chip receiving a dose greater than about 12 megarads.

13. The device of claim 9, wherein said chip is irradiated to reduce lifetime;

said chip receiving a dose greater than about 12 megarads.

14. The device of claim 10, wherein said chip is irradiated to reduce lifetime;

said chip receiving a dose greater than about 12 megarads.

15. The device of claim 11, wherein said chip has heavy metal atoms therein to kill lifetime.

16. The device of claim 9, wherein said chip has heavy metal atoms therein to kill lifetime.

17. The device of claim 10, wherein said chip has heavy metal atoms therein to kill lifetime.

27. The device of claim 1, wherein said increased concentration of carriers extend to a uniform depth over the full active area of said devices beneath said base regions and terminates at the surface of said chip.

28. The device of claim 11, wherein said regions of increased concentration extend to a uniform depth over the full active area of said devices beneath said bases and terminate at the surface of said chip.

18. A power transistor device;

said device comprising a thin chip of semiconductor material having a substrate and a lightly doped layer of semiconductor material of one conductivity type disposed atop one surface of said substrate, a plurality of spaced base regions of the opposite conductivity type extending into the opposite surface of said layer of semiconductor material to a given depth, a plurality of source regions of said one conductivity type formed in respective ones of said plurality of spaced base regions and defining respective surface channel regions, a gate insulation layer disposed over said channel regions, a conductive gate layer disposed over said gate insulation layer, a source electrode connected to said plurality of source regions and a drain electrode connected to said substrate;

said spaced base regions being so closely spaced as to define a highly efficient parasitic JFET when using a doping concentration between said spaced base regions of the value of the concentration of said layer of semiconductor material;

the regions between said spaced base regions having an increased concentration of carriers of said one conductivity type which extends from said surface of said layer to a depth greater than the depth of said base regions and having a conductivity greater than that of the remaining portion of said layer.

19. The device of claim 18, wherein said regions of increased concentration are formed by an implant dose of greater than about 3×

10¹² atoms per square centimeter of a dopant of said one conductivity type followed by a diffusion for about 10 hours at about 1175°

C.

20. The device of claim 18, wherein said regions of increased concentration have a depth greater than about 6 microns.

21. The device of claim 18, wherein said base regions have a cellular topology.

22. The device of claim 21, wherein said cellular base regions have a hexagonal geometry.

23. The device of claim 18, wherein a further layer of said opposite conductivity type, which is more highly doped than said lightly doped layer and which is thinner than said lightly doped layer, is disposed between said layer and said substrate.

24. The device of claim 18, wherein the bottoms of said regions of increased concentration of carriers which extend deeper than said bases define a symmetrical pattern in conformance with the perimeter of said deep bases and facing said drain electrode and, define an enlarged preferential avalanche breakdown voltage area to increase the I² L capability of said device.

25. The device of claim 18, wherein said chip is irradiated to reduce lifetime;

said chip receiving a dose greater than about 12 megarad.

26. The device of claim 18, wherein said chip has heavy metal atoms therein to kill lifetime.

29. A power transistor device comprising a substrate of one conductivity type, a lightly doped layer of semiconductor material of the opposite conductivity type disposed atop one surface of said substrate, a plurality of spaced base regions of said one conductivity type extending into the opposite surface of said layer of semiconductor material to a given depth, a plurality of source regions of said opposite conductivity type formed in respective ones of said plurality of spaced base regions and defining respective surface channel regions therebetween, a gate insulation layer disposed over said channel regions, a conductive gate layer disposed over said gate insulation layer, a first main electrode connected to said plurality of source regions and a second main electrode connected to said substrate, the regions between said spaced base regions having an increased concentration of carriers of said opposite conductivity type which extends from said opposite surface to a depth greater than the depth of said base regions;

said increased concentration being greater than that of the remaining portion of said layer of semiconductor material over its full depth.

30. A power transistor device having bipolar device forward current carrying characteristics and MOS gate control characteristics;

said device comprising a substrate of a first conductivity type, a lightly doped layer of semiconductor material of a second opposite conductivity type disposed atop one surface of said substrate, a plurality of spaced base regions of said first conductivity type extending into the opposite surface of said layer of semiconductor material to a given depth, a plurality of source regions of said second conductivity type formed in respective ones of said plurality of spaced base regions defining respective surface channel regions, a gate insulation layer disposed over said channel regions, a conductive gate layer disposed over said gate insulation layer, a first main electrode connected to said plurality of source regions and a second main electrode in electrical connection with said layer of semiconductor material of the second conductivity type through a region of said first conductivity type, the regions between said spaced base regions having an increased concentration of carriers of said second conductivity type which extends from said opposite surface to a depth greater than the depth of said base regions;

said increased concentration being greater than that of the remaining portion of said of semiconductor material over its full depth.

31. The device of claim 30, wherein the region of said first conductivity type through which the second main electrode is in electrical connection with said layer of semiconductor material of said second conductivity type comprises the substrate.