Bidirectional blocking accumulation-mode trench power MOSFET

• US 5,661,322 A
• Filed: 06/02/1995
• Issued: 08/26/1997
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Mallikarjunaswamy, Shekar S.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/459,559
• Time in Patent Office: 816 Days
• Field of Search: 257/327, 257/329, 257/330, 257/331
• US Class Current: 257/331
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 7/003 Constructional details, e.g. physical layout, assembly, wiring or busbar connections
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches
• CPC Class Codes: H03K 17/08142 in field-effect transistor switches
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit

Abstract

One or more diodes are integrated with a trenched gate accumulation-mode MOSFET to provide protection for the gate oxide layer. In a preferred embodiment, a first pair of diodes are formed in a series connection between the source and the gate of the MOSFET. A third diode may be added to provide a series diode pair between the drain and the gate of the MOSFET. A pair of accumulation-mode MOSFETs may be formed in a single chip to provide a push-pull halfbridge circuit, and a multiple-phase motor driver may be fabricated in two chips, with the high side MOSFETs being formed in one chip and the low side MOSFETs being formed in the other chip. The accumulation-mode MOSFET may be used as an AC switch by connecting its gate to a gate bias circuit which finds the lower of the source and drain voltages of the accumulation-mode MOSFET.

Claims

1. An accumulation-mode MOSFET comprising:

a semiconductor chip;

a gate formed in a trench at a surface of said semiconductor chip and separated from said semiconductor chip by an insulating layer, said trench defining a cell of said MOSFET, a first region of said semiconductor chip being located within said cell and containing semiconductor material of a first conductivity type, said cell being designed such that a substantial portion of said first region is depleted thereby preventing the flow of current through said first region when said gate is held at a predetermined voltage;

a second region of said first conductivity type located under said trench;

a third region of a second conductivity type adjacent said second region, a junction between said second and third regions forming a first diode; and

a fourth region of said first conductivity type adjacent said third region, a junction between said third and fourth regions forming a second diode, wherein said fourth region is connected to said gate.

2. The MOSFET of claim 1 further comprising a fifth region of said first conductivity type adjacent said third region, a junction between said third and fifth regions forming a third diode, wherein said fifth region is connected to said first region.

27. The accumulation-mode MOSFET of claim 1 or 2 wherein said first region comprises a heavily-doped source region adjacent said surface and a lightly-doped drift region adjacent said source region.

28. The accumulation-mode MOSFET of claim 1 or 2 wherein said second region comprises a drain region having a contact on an opposite surface of said chip.

29. The accumulation-mode MOSFET of claim 1 wherein said third and fourth regions are located on an opposite side of said trench from said first region.

30. The accumulation-mode MOSFET of claim 2 wherein said third, fourth and fifth regions are located on an opposite side of said trench from said first region.

4. An accumulation-mode field-effect transistor (MOSFET) comprising:

a semiconductor material;

a gate positioned in a trench at a surface of said semiconductor material and separated from said semiconductor material by a gate insulating layer, said trench defining a transistor cell, said cell containing substantially only material of a first conductivity type;

a first heavily-doped region of said first conductivity type located at a surface of said cell;

a lightly-doped region of said first conductivity type adjacent said heavily-doped region;

a first PN junction within said semiconductor material, said first PN junction forming a first diode; and

a second PN junction within said semiconductor material, said second PN junction forming a second diode, said first and second diodes being connected in series between said heavily doped region and said gate.

3. The MOSFET of claim 4 wherein said first and second diodes are connected back-to-back.

5. The MOSFET of claim 4 wherein said first diode is connected between said gate and a second heavily-doped region of said first conductivity type, said second heavily-doped region being located in said semiconductor material below said trench.

6. The MOSFET of claim 5 further comprising a third PN junction within said semiconductor material, said third PN junction forming a third diode, said third diode being connected in series with said first diode between said second heavily-doped region and said gate.

7. A halfbridge circuit formed in a semiconductor chip, said halfbridge circuit comprising:

a first accumulation-mode MOSFET, said first accumulation-mode MOSFET comprising a first trenched gate, a first heavily-doped region of a first conductivity type located at a surface of said chip, a second lightly-doped region of said first conductivity type located below said first region, and a third heavily-doped region of said first conductivity type located below said second lightly-doped region;

a second accumulation-mode MOSFET, said second accumulation-mode MOSFET comprising a second trenched gate, a fourth heavily-doped region of said first conductivity type located at a surface of said chip, a fifth lightly-doped region of said first conductivity type located below said fourth region, and said third heavily-doped region of said first conductivity type;

a first voltage supply connected to said first heavily-doped region and a second voltage supply connected to said fourth heavily-doped region; and

an output terminal connected to said third heavily-doped region.

8. The halfbridge circuit of claim 7 further comprising:

a sixth region of a second conductivity type, a junction of said sixth region forming a first diode, said first diode being connected in parallel with said first accumulation-mode MOSFET; and

a seventh region of said second conductivity type, a junction of said seventh region forming a second diode, said second diode being connected in parallel with said second accumulation-mode MOSFET.

9. The halfbridge circuit of claim 8 wherein said first diode is formed at a junction of said second and sixth regions.

10. The halfbridge circuit of claim 8 wherein said second diode is formed at a junction of said seventh region and an eighth region of said first conductivity type.

11. The halfbridge circuit of claim 7 wherein said second and fifth regions are contiguous.

12. The halfbridge circuit of claim 7 wherein said first, second, fourth and fifth regions are part of an epitaxial layer.

13. The halfbridge circuit of claim 12 wherein said third region is included in a substrate.

14. The halfbridge circuit of claim 8 wherein said seventh region is connected to said third region.

15. The halfbridge circuit of claim 10 further comprising a ninth region of said first conductivity type located at a surface of said chip, said ninth region being adjacent said third region, said seventh region being connected to said ninth region.

16. A multiple-phase motor driver comprising:

a first chip, said first chip comprising a plurality of high side accumulation-mode MOSFETs; and

a second chip, said second chip comprising a plurality of low side accumulation-mode MOSFETs;

wherein a substrate of said first chip is connected to a first voltage source and a substrate of said second chip is connected to a second voltage source, and wherein a first MOSFET in said first chip is connected to a first MOSFET in said second chip and to a first output terminal, and a second MOSFET in said first chip is connected to a second MOSFET in said second chip and to a second output terminal.

17. The multiple-phase motor drive of claim 16 further comprising a first diode formed in said first chip, said first diode being connected in parallel with said first MOSFET in said first chip.

18. The multiple-phase motor drive of claim 17 wherein said first diode is formed at a junction of a first region and said substrate, said substrate being doped with a dopant of a first conductivity type and said first region being doped with a dopant of a second conductivity type.

19. The multiple-phase motor drive of claim 18 wherein said first region is connected to said first output terminal.

20. The multiple-phase motor drive of claim 19 wherein said first region is connected to said first output terminal via a second region of a second conductivity type located at a surface of said first chip, said first and second regions being shorted together.

21. The multiple-phase motor drive of claim 16 further comprising a first diode formed in said second chip, said first diode being connected in parallel with said first MOSFET in said second chip.

22. The multiple-phase motor drive of claim 21 wherein said first diode is formed at a junction of a first region of a first conductivity type and a second region of a second conductivity type.

23. The multiple-phase motor drive of claim 22 wherein said first region is located at a surface of said second chip and said second region is shorted to said substrate of said second chip.

24. An accumulation-mode MOSFET comprising:

a semiconductor chip of a first conductivity type;

a trenched gate formed in said chip, said gate defining a MOSFET cell, said gate comprising a first region doped with a dopant of said first conductivity type, a second region adjacent said first region and doped with a dopant of a second conductivity type, and a third region adjacent said second region and doped with a dopant of said first conductivity type;

wherein said third region is connected to a surface of said MOSFET cell.

25. The accumulation-mode MOSFET of claim 24 wherein said gate further comprises a fourth region adjacent said first region and doped with a dopant of said second conductivity type, and a fifth region adjacent said fourth region and doped with a dopant of said first conductivity type and wherein said fifth region is connected to a backside of said semiconductor chip.

26. An accumulation-mode MOSFET comprising:

a semiconductor chip of a first conductivity type;

a trenched gate formed in said chip, said gate defining a MOSFET cell, said gate comprising a first region doped with a dopant of said first conductivity type, a second region adjacent said first region and doped with a dopant of a second conductivity type, and a third region adjacent said second region and doped with a dopant of said first conductivity type;

wherein said third region is connected to a backside of said semiconductor chip.

31. An accumulation-mode field-effect transistor (MOSFET) comprising:

a semiconductor material;

a gate positioned at least partially in a trench formed at a surface of said semiconductor material, said gate being separated from said semiconductor material by a gate insulating layer, said trench defining a transistor cell, said cell containing substantially only material of a first conductivity type;

a first heavily-doped region of said first conductivity type located at a surface of said cell;

a lightly-doped region of said first conductivity type adjacent said heavily-doped region;

a second heavily-doped region of said first conductivity type located in said semiconductor material below said trench;

wherein said gate is formed of polysilicon, said polysilicon being doped so as to form first and second diodes in said gate, said first and second diodes being connected in series between a portion of said gate within said trench and said first heavily-doped region.

32. The MOSFET of claim 31 wherein said first and second diodes are connected back-to-back.

33. The MOSFET of claim 31 wherein said polysilicon is doped so as to form third and fourth diodes in said gate, said third and fourth diodes being connected in series between said portion of said gate within said trench and a third heavily-doped region of said first conductivity type, said third heavily-doped region being coupled to said second heavily-doped region.

34. The MOSFET of claim 33 wherein said third and fourth diodes are connected back-to-back.

35. An accumulation-mode field-effect transistor (MOSFET) comprising:

a semiconductor material;

a gate positioned at least partially in a trench formed at a surface of said semiconductor material, said gate being separated from said semiconductor material by a gate insulating layer, said trench defining a transistor cell, said cell containing substantially only material of a first conductivity type;

a first heavily-doped region of said first conductivity type located at a surface of said cell;

a lightly-doped region of said first conductivity type adjacent said heavily-doped region;

a second heavily-doped region of said first conductivity type located in said semiconductor material below said trench;

wherein said gate is formed of polysilicon, said polysilicon being doped so as to form first and second diodes in said gate, said first and second diodes being connected in series between a portion of said gate within said trench and third heavily-doped region of said first conductivity type, said third heavily-doped region being coupled to said second heavily-doped region.

36. The MOSFET of claim 35 wherein said first and second diodes are connected back-to-back.