Integrated circuit fuse programming and reading circuits

• US 5,661,323 A
• Filed: 06/27/1996
• Issued: 08/26/1997
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Yi, Jeong-Hyong, Choi, Jeong-Hyuk, Kim, Dong-Jun
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/670,506
• Time in Patent Office: 425 Days
• Field of Search: 257/529, 257/530, 257/528, 257/774, 257/786, 257/536, 257/378, 257/379, 327/525, 365/177, 365/225.7
• US Class Current: 257/378
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit fuse circuit includes a plurality of fuses each connected to an output terminal, and a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage. Each of the fuse programming circuits includes a pair of complementary bipolar transistors and a field effect transistor. The pair of complementary bipolar transistors produce a large current through the associated fuse in response to a fuse programming signal which is applied to the field effect transistor. The fuse programming circuit may be fabricated in an integrated circuit by providing first and second spaced apart regions of second conductivity type in a well of first conductivity type, and a third region of the first conductivity type in the first region. An insulated gate is provided on the face between the first and second spaced apart regions. An insulated fuse is also provided on the face, electrically connected to the third region.

Claims

1. An integrated circuit fuse circuit comprising:

a plurality of fuses, each connected to an output terminal;

a plurality of fuse programming and reading circuits, a respective one of which is connected between a respective fuse and a reference voltage, each of said fuse programming and reading circuits comprising;

a first bipolar transistor having a controlling electrode and a pair of controlled electrodes;

a second bipolar transistor and a first field effect transistor each having a controlling electrode and a pair of controlled electrodes, the controlled electrodes of both of which are connected in parallel between the controlling electrode of said first bipolar transistor and said reference voltage; and

a second field effect transistor having a controlling electrode and a pair of controlled electrodes, the controlled electrodes of said second field effect transistor being connected between the controlling electrode of said first bipolar transistor and a reference voltage;

the controlled electrodes of said first bipolar transistor being connected between the associated fuse and the controlling electrode of said second bipolar transistor.

2. An integrated circuit fuse circuit according to claim 1 further comprising a load transistor, having a controlling electrode and a pair of controlled electrodes, the controlled electrodes being connected between a power supply voltage and said output terminal.

3. An integrated circuit fuse circuit according to claim 1 wherein a fuse programming signal is applied to the controlling electrode of the first field effect transistor of a fuse programming circuit which is connected to a fuse to be programmed.

4. An integrated circuit fuse circuit according to claim 1 wherein a fuse programming signal is applied to the controlling electrode of the first field effect transistor of a fuse programming circuit which is connected to a fuse to be programmed, and wherein a fuse reading signal is applied to the controlling electrode of the second field effect transistor which is connected to a fuse to be read.

9. An integrated circuit fuse circuit according to claim 1 wherein each of said fuses comprises:

an elongated insulated conductive layer, said elongated insulated conductive layer comprising a pair of spaced apart relatively wide contact regions and a relatively narrow elongated fuse region extending therebetween and connected thereto, wherein said pair of contact regions connect to said elongated fuse region at an angle of between eighty five degrees and ninety five degrees.

5. An integrated circuit fuse circuit comprising:

a plurality of fuses, each connected to an output terminal;

a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage, each of said fuse programming circuits comprising;

a first bipolar transistor having a controlling electrode and a pair of controlled electrodes; and

a second bipolar transistor and a first field effect transistor each having a controlling electrode and a pair of controlled electrodes, the controlled electrodes of both of which are connected in parallel between the controlling electrode of said first bipolar transistor and said reference voltage;

the controlled electrodes of said first bipolar transistor being connected between the associated fuse and the controlling electrode of said second bipolar transistor;

wherein the emitter of a respective first bipolar transistor is connected to a respective fuse;

wherein a respective collector and base of a respective second bipolar transistor is connected to a respective base and collector of a respective first bipolar transistor;

wherein the drain of a respective first field effect transistor is connected to the base of a respective first bipolar transistor; and

wherein the emitters of said second bipolar transistors and the sources of said first field effect transistors are connected to ground potential.

6. An integrated circuit fuse circuit comprising:

a plurality of fuses, each connected to an output terminal;

a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage, each of said fuse programming circuits comprising;

a first bipolar transistor having a controlling electrode and a pair of controlled electrodes; and

a second bipolar transistor and a first field effect transistor each having a controlling electrode and a pair of controlled electrodes, the controlled electrodes of both of which are connected in parallel between the controlling electrode of said first bipolar transistor and said reference voltage;

the controlled electrodes of said first bipolar transistor being connected between the associated fuse and the controlling electrode of said second bipolar transistor; and

wherein each of said fuses and fuse circuits comprises;

a well of first conductivity type in a semiconductor substrate, at a face thereof;

first and second spaced apart regions of second conductivity type in said well, at said face;

a third region of said first conductivity type in said first region at said face;

an insulated gate on said face, between said first and second spaced apart regions; and

an insulated fuse on said face, electrically connected to said third region;

wherein said well and said first and third regions define said first bipolar transistor;

wherein said first and second spaced apart regions and said insulated gate therebetween define said first field effect transistor; and

wherein said first and second spaced apart regions and said well define said second bipolar transistor.

7. An integrated circuit fuse circuit according to claim 6 wherein said well is located in a second well of second conductivity type in said semiconductor substrate.

8. An integrated circuit according to claim 6 wherein said insulated fuse comprises:

an elongated insulated conductive layer on said substrate, said elongated insulated conductive layer comprising a pair of spaced apart relatively wide contact regions and a relatively narrow elongated fuse region extending therebetween and connected thereto, said elongated fuse region defining transition edges in said pair of contact regions where said elongated fuse region connects to said contact regions, said transition edges extending from said relatively narrow fuse region to said relatively wide contact regions at an angle of between eighty five degrees and ninety five degrees.

10. An integrated circuit fuse circuit comprising:

a plurality of fuses, each connected to an output terminal;

a plurality of fuse programming circuits, a respective one of which is connected between a respective fuse and a reference voltage, each of said fuse programming circuits comprising a pair of complementary bipolar transistors, a first field effect transistor and a second field effect transistor, wherein said pair of complementary bipolar transistors produce a programming current through the respective fuse in response to a fuse programming signal which is applied to said first field effect transistor, and wherein a state of the respective fuse is read by detecting a reading current through said fuse in response to a fuse read signal which is applied to said second field effect transistor.

11. An integrated circuit fuse circuit according to claim 10 further comprising a load transistor connected between a power supply voltage and said output terminal.

12. An integrated circuit fuse circuit comprising:

a fuse; and

a fuse programming circuit connected to said fuse and comprising a pair of complementary bipolar transistors, a first field effect transistor and a second field effect transistor, wherein said pair of complementary bipolar transistors produce a programming current through said fuse in response to a fuse programming signal which is applied to said first field effect transistor, and wherein a state of said fuse is read by determining if a read current flows through said fuse in response to a fuse read signal which is applied to said second field effect transistor.

13. A fuse cell for an integrated circuit comprising:

a semiconductor substrate;

a well of first conductivity type in said semiconductor substrate, at a face thereof;

first and second spaced apart regions of second conductivity type in said well, at said face;

a third region of said first conductivity type in said first region at said face;

an insulated gate on said face, between said first and second spaced apart regions; and

an insulated fuse on said face, electrically connected to said third region.

14. A fuse cell according to claim 13:

wherein said well and said first and third regions define a first bipolar transistor;

wherein said first and second spaced apart regions and said insulated gate therebetween define a field effect transistor; and

wherein said first and second spaced apart regions and said well define a second bipolar transistor.

15. A fuse cell according to claim 13 wherein said well is located in a second well of second conductivity type in said semiconductor substrate.

16. A fuse cell according to claim 13 wherein said insulated fuse comprises:

an elongated insulated conductive layer on said substrate, said elongated insulated conductive layer comprising a pair of spaced apart relatively wide contact regions and a relatively narrow elongated fuse region extending therebetween and connected thereto, said elongated fuse region defining transition edges in said pair of contact regions where said elongated fuse region connects to said contact regions, said transition edges extending from said relatively narrow fuse region to said relatively wide contact regions at an angle of between eighty five degrees and ninety five degrees.

17. A fuse cell for an integrated circuit comprising:

a semiconductor substrate;

a well of first conductivity type in said semiconductor substrate, at a face thereof;

first and second spaced apart regions of second conductivity type in said well, at said face;

an insulated gate on said face, between said first and second spaced apart regions; and

an insulated fuse on said face, electrically connected to said first region;

wherein said well is located in a second well of second conductivity type in said semiconductor substrate.