Output buffer circuit with logic gate control circuitry

• US 5,661,415 A
• Filed: 02/28/1996
• Issued: 08/26/1997
• Est. Priority Date: 03/06/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Aoki, Yasushi, Katayama, Atsushi
• Primary Examiner(s): Hudspeth, David R.
• Application Number:
  US08/608,318
• Time in Patent Office: 545 Days
• Field of Search: 326/27, 326/34, 326/82-83, 326/86
• US Class Current: 326/82
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance
• CPC Class Codes: H03K 19/01707 in asynchronous circuits

Abstract

The present invention has the object of improving operation speed and operation margin for a GTL driver. An output buffer circuit is of push-pull construction using N-channel MOS transistors MN11 and MN12. An output signal is fed back to pull-up transistor MN11 by way of NOR circuit NOR1, and a low-amplitude, high-speed signal waveform is outputted. The output of this output buffer circuit is inputted to a differential input circuit of another semiconductor integrated circuit. The reference input of the differential input circuit is connected to a reference voltage supply, and the input of the differential input circuit is terminated to the reference voltage supply by terminating resistance. By means of this configuration, the input amplitude of the differential input circuit oscillates with respect to the reference voltage without being affected by the power supply voltage of the output buffer circuit, the power supply voltage of the differential input circuit, or power-supply fluctuations of the reference voltage, thereby broadening the margin against noise.

Claims

1. An output buffer circuit comprising:

an input terminal for inputting internal signals of a semiconductor integrated circuit;

an output terminal for outputting signals to outside the semiconductor integrated circuit;

first and second N-channel MOS transistors; and

a control circuit for controlling operation of said first N-channel MOS transistor by signals inputted from said input terminal and signals outputted from said output terminal;

said control circuit switching either said first or second N-channel MOS transistor into conduction.

2. An output buffer circuit according to claim 1 wherein:

said control circuit further is a NOR circuit having one input terminal connected to said input terminal and its other input terminal connected to said output terminal;

said first N-channel MOS transistor has its source terminal connected to a power supply, its gate terminal connected to the output terminal of said NOR circuit, and its drain terminal connected to said output terminal; and

the second N-channel MOS transistor has its gate terminal connected to said input terminal, its drain terminal connected to said output terminal, and its source terminal connected to ground.

3. An output buffer circuit according to claim 2 wherein said NOR circuit further comprises:

a third N-channel MOS transistor having its gate terminal connected to said input terminal, its drain terminal connected to the gate terminal of said first N-channel MOS transistor, and its source terminal connected to ground;

a fourth N-channel MOS transistor having its gate terminal connected to said output terminal, its drain terminal connected to the gate terminal of said first N-channel MOS transistor, and its source terminal connected to ground;

a first P-channel MOS transistor having its gate terminal connected to said input terminal, and its source terminal connected to a power supply; and

a second P-channel MOS transistor having its gate terminal connected to said output terminal, its source terminal connected to the drain terminal of said first P-channel MOS transistor, and its drain terminal connected to the gate terminal of said first N-channel MOS transistor.

4. An output buffer circuit according to claim 2 wherein said NOR circuit further comprises:

a third N-channel MOS transistor having its gate terminal connected to said input terminal, its drain terminal connected to the gate terminal of said first N-channel MOS transistor, and its source terminal connected to ground;

a fourth N-channel MOS transistor having its gate terminal connected to said output terminal, its drain terminal connected to the gate terminal of said first N-channel MOS transistor, and its source terminal connected to ground; and

a first P-channel MOS transistor having its gate terminal connected to said input terminal, its drain terminal connected to the gate terminal of said first N-channel MOS transistor, and its source terminal connected to a power supply.

5. A transmitter using an output buffer circuit according to claim 1, comprising:

a transmission line connected to the output terminal of said output buffer circuit;

a differential input circuit having one input terminal connected to said output buffer circuit by way of said transmission line, and its other input terminal connected to a constant-voltage source; and

resistance connected between the two input terminals of said differential input circuit.

6. An output buffer circuit comprising:

an input terminal and an output terminal;

a NOR circuit having a first input connected to said input terminal and a second input connected to said output terminal;

a first N-channel MOS transistor with a source connected to a power supply, a drain connected to said output terminal and a gate connected to an output from said NOR circuit; and

a second N-channel MOS transistor with a source connected to a ground, a drain connected to said output terminal and a gate connected to said input terminal,

said NOR circuit for switching either said first or second N-channel MOS transistor into conduction.

7. A transmitter using the output buffer circuit according to claim 6 and further comprising:

a transmission line connected to said output terminal;

a differential input circuit having one input connected to said transmission line and a further input connected to a reference voltage; and

a resistance connected between said inputs of said differential input circuit.

8. A transmitter comprising:

an output buffer circuit having (a) an input terminal and an output terminal, (b) first and second MOS transistors, (c) a control circuit for switching said first MOS transistor into conduction with signals at a first control circuit input which is connected to said input terminal and at a second control circuit input which is connected to said output terminal and for switching said second MOS transistor into conduction when said first MOS transistor is not switched into conduction;

a transmission line connected to said output terminal;

a differential input circuit having one input connected to said transmission line and a further input connected to a reference voltage; and

a resistance connected between said inputs of said differential input circuit.

9. The transmitter of claim 8 wherein said control circuit is a NOR circuit having an output connected to a gate of said first MOS transistor.