Structures and methods for adding stimulus and response functions to a circuit design undergoing emulation

• US 5,661,662 A
• Filed: 06/06/1995
• Issued: 08/26/1997
• Est. Priority Date: 10/05/1988
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Butts, Michael R., Batcheller, Jon A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/471,679
• Time in Patent Office: 812 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578, 395/500, 326/39, 326/41, 340/825.83
• US Class Current: 326/37
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims

1. An electrically reconfigurable hardware emulation apparatus which can be configured with a logic circuit design, said electrically reconfigurable hardware emulation apparatus comprising:

a plurality of electrically reconfigurable devices, at least some of said electrically reconfigurable devices containing reprogrammable functional logic elements and input/out terminals capable of being connected to at least some of said functional logic elements, said plurality of electrically reconfigurable devices further comprising stimulators and samplers, said stimulators providing input signals to the circuit design undergoing emulation, said samplers collecting output signals from the circuit design undergoing emulation which said emulation system generates in response to said input signals;

at least one other of said electrically reconfigurable devices containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of selected electrically reconfigurable devices containing functional logic elements such that selected functional logic elements in one of said selected electrically reconfigurable devices containing functional logic elements can be electrically coupled to selected functional logic elements in an other of said selected electrically reconfigurable devices containing functional logic elements; and

a set of fixed electrical conductors connecting said input/output terminals on said electrically reconfigurable devices containing reprogrammable functional logic elements to input/output terminals on said electrically reconfigurable devices containing reprogrammable electrical conductors.