Analog output buffer circuit
First Claim
1. An output buffer circuit having a low quiescent power dissipation and a high current-drive capability, said output buffer circuit comprising:
- a first transistor coupling between a power supply and an output, wherein the gate of said first transistor is connected to an input signal;
a second transistor coupling between said output and a ground;
a capacitor coupling between a gate of said first transistor and a gate of said second transistor, wherein voltages at said gate of said first transistor are related to voltages at said gate of said second transistor via said capacitor; and
a third transistor coupling between said gate of said second transistor and a current source.
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Abstract
An analog output buffer circuit having a low quiescent power dissipation and a high current-driving capability is disclosed. In accordance with a preferred embodiment of the present invention, the analog output buffer circuit includes a capacitor and three transistors. The first transistor is coupled between a power supply and an output. The gate of the first transistor is utilized for receiving input signals. The second transistor is coupled between the output and ground. The capacitor is coupled between a gate of the first transistor and a gate of the second transistor such that voltages at the gate of the first transistor are related to voltages at the gate of the second transistor via the capacitor. Finally, the third transistor is coupled between the gate of the second transistor and a current source. This configuration allows the analog output buffer circuit to have a high current-driving capability while maintaining a low power dissipation during the quiescent period.
7 Citations
15 Claims
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1. An output buffer circuit having a low quiescent power dissipation and a high current-drive capability, said output buffer circuit comprising:
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a first transistor coupling between a power supply and an output, wherein the gate of said first transistor is connected to an input signal; a second transistor coupling between said output and a ground; a capacitor coupling between a gate of said first transistor and a gate of said second transistor, wherein voltages at said gate of said first transistor are related to voltages at said gate of said second transistor via said capacitor; and a third transistor coupling between said gate of said second transistor and a current source. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An output buffer circuit having a low quiescent power dissipation and a high current-driving capability, said output buffer circuit comprising:
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a first transistor and a second transistor coupling in series between a power supply and a ground, wherein a gate of said first transistor is connected to an input signal, wherein an output is located between said first transistor and said second transistor; a capacitor coupling between a gate of said first transistor and a gate of said second transistor; a forth transistor and a fifth transistor coupling in series between said power supply and said ground, wherein a gate and a drain of said fifth transistor are connected together; and a third transistor coupling between said gate of said second transistor and said gate of said fifth transistor. - View Dependent Claims (8, 9, 10)
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11. A disk drive comprising:
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a disk mounted for rotation and having burst signals recorded on a surface thereof to provide location information; a read/write head mounted for movement over said surface of said disk to read said burst signals; at least one peak-hold circuit for receiving said burst signals from said read/write head; at least one output buffer circuit for transferring said burst signals from said at least one peak-hold circuit to a corresponding load capacitor, wherein each of said at least one output buffer circuit further includes a first transistor coupling between a power supply and an output, wherein a gate of said first transistor is for receiving said burst signals; a second transistor coupling between said output and a ground; a capacitor coupling between a gate of said first transistor and a gate of said second transistor, wherein voltages at said gate of said first transistor are related to voltages at said gate of said second transistor via said capacitor; and a third transistor coupling between said gate of said second transistor and a current source. - View Dependent Claims (12, 13, 14, 15)
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Specification