Radio-card communication system

• US 5,661,757 A
• Filed: 03/17/1995
• Issued: 08/26/1997
• Est. Priority Date: 03/18/1994
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Takahashi, Yasuo, Gunji, Tatsuya, Oyama, Masumi
• Primary Examiner(s): TSE, YOUNG TOI
• Application Number:
  US08/405,893
• Time in Patent Office: 893 Days
• Field of Search: 375/219, 375/279-281, 375/283, 375/308, 375/324-325, 375/326, 375/329-332, 375/344-345, 329/304, 329/306
• US Class Current: 375/281
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/0008 General problems related to the reading of electronic memory record carriers, independent of its reading method, e.g. power transfer

Abstract

To receive a response signal from a radio card, a card reader transmits a carrier (not modulated) to the radio card. In the radio card, a phase modulator phase-modulates the a sub-carrier with a response signal, thereby generating a PSK signal, and a phase modulator phase-modulates the carrier with the PSK signal, producing a PSK-PSK signal. The PSK-PSK signal is supplied to an antenna via a signal-extracting device. The antenna sends the PSK-PSK signal toward the card reader. In the card reader, a distributor distributes the PSK-PSK signal to a synchronous detector and an orthogonal detector. The detectors performs synchronous detection by using carriers which differ in phase by 90°. Low-pass filters extract sub-carrier components from the outputs of the detectors. The sub-carrier components are delayed and detected by delay detectors and added together by an adder. The level of the output of the adder is determined by a data discriminator, whereby the card reader obtains the response signal transmitted from the radio card.

Claims

1. A radio-card communications system having a radio card for transmitting a response signal in response to a question signal, and a card reader for transmitting the question signal and receiving the response signal,

said radio card comprising:

carrier-receiving means for receiving a carrier transmitted from said card reader;

sub-carrier generating means for generating a sub-carrier having a frequency lower than a frequency of the carrier;

first phase-modulating means for phase-modulating the sub-carrier with the response signal, thereby to generate a PSK signal;

second phase-modulating means for phase-modulating the carrier with the PSK signal, thereby to generate a PSK-PSK signal; and

PSK-PSK signal transmitting means for transmitting the PSK-PSK signal to said card reader; and

said card reader comprising;

carrier-transmitting means for transmitting the carrier to said radio card in response to the response signal;

PSK-PSK signal receiving means for receiving the PSK-PSK signal from said radio card;

sub-carrier extracting means for performing orthogonal detection on the PSK-PSK signal, thereby to extract a sub-carrier component; and

demodulating means for extracting a phase-modulated component from the sub-carrier component, thereby to demodulate the response signal.

2. The system according to claim 1, wherein said radio card further comprises:

an exclusive logic-sum circuit for obtaining an exclusive logic sum of data about said response signal and other data and a delay circuit for delaying an output of said exclusive logic-sum circuit by a preset time, and wherein an output of said delay circuit is input to said exclusive logic-sum circuit, a logic sum obtained by said logic-sum circuit is supplied to said first phase-modulating means.

3. The system according to claim 2, wherein said sub-carrier extracting means comprises first and second synchronous detectors for detecting the PSK-PSK signal by using, respectively, an in-phase reference signal and an orthogonal reference signal 90°

out of phase with respect to the in-phase reference signal, and first and second filters for extracting sub-carrier components from signals detected by said first and second synchronous detectors; and

said demodulating means comprises first and second delay detectors for detecting outputs of said first and second filters, respectively, thereby to extract the phase-modulated components, an adder for adding outputs of said delay detectors, and a data discriminator for discriminating the data about the response signal in accordance with an output level of said adder.

4. The system according to claim 3, wherein each of said delay detectors comprises a distributor for distributing the sub-carrier component in the form of first and second outputs, a delay circuit for delaying the first output by the preset time, a multiplier for multiplying an output of said delay circuit by the second output of said distributor, and a filter circuit for extracting a phase-modulated component from an output of said multiplier.

5. The system according to claim 2, wherein said sub-carrier extracting means comprises first and second synchronous detectors for detecting the PSK-PSK signal by using, respectively, an in-phase reference signal and an orthogonal reference signal 90°

out of phase with respect to the in-phase reference signal, and first and second filters for extracting sub-carrier components from signals detected by said first and second synchronous detectors; and

said demodulating means comprises first and second A/D converters for converting, respectively, outputs of said first and second filters to digital signals, first and second digital delay detectors for detecting and delaying, respectively, outputs of said first and second A/D converters, thereby to extract the phase-modulated components, a digital adder for adding outputs of said digital delay detectors, and said demodulating means outputs, as said response signal, a data bit contained in an output of said digital adder and representing a polarity of the output of said digital adder.

6. The system according to claim 5, wherein each said digital delay detector comprises a delay memory for delaying an input digital signal by the preset time, a multiplier receiving and multiplying an output of said delay memory and said input digital signal, and a digital filter for extracting a phase-modulated component from an output of said multiplier.

7. The system according to claim 2, wherein said sub-carrier extracting means comprises first and second synchronous detectors for detecting the PSK-PSK signal by using, respectively, an in-phase reference signal and an orthogonal reference signal 90°

out of phase with respect to the in-phase reference signal, and first and second filters for extracting sub-carrier components from signals detected by said first and second synchronous detectors; and

said demodulating means comprises first and second A/D converters for converting, respectively, outputs of said first and second filters to digital signals, a multiplexer for alternately selecting outputs of the first and second A/D converters, and a digital delay detector for detecting and delaying an output of said multiplexer, thereby to extract a phase-shifted component, and said demodulating means outputs, as said response signal, a data bit contained in an output of said digital delay detector and representing a polarity of the output of said digital delay detector.

8. The system according to claim 2, wherein said sub-carrier extracting means comprises first and second synchronous detectors for detecting the PSK-PSK signal by using, respectively, an in-phase reference signal and an orthogonal reference signal 90°

out of phase with respect to the in-phase reference signal, and first and second filters for extracting sub-carrier components from signals detected by said first and second synchronous detectors; and

said demodulating means comprises a multiplexer for alternately selecting outputs of the first and second filters, an A/D converter for converting, respectively, an output of said multiplexer, and a digital delay detector for detecting and delaying an output of said D/A converter, thereby to extract a phase-shifted component, and said demodulating means outputs, as said response signal, a data bit contained in an output of said digital delay detector and representing a polarity of the output of said digital delay detector.

9. The system according to any one of claims 7-8 wherein said digital delay detector comprises a delay memory for delaying an input digital signal by the preset time, a multiplier receiving and multiplying an output of said delay memory and said input digital signal, and a digital filter for extracting a phase-modulated component from an output of said multiplier.