Method for mounting and electrically interconnecting semiconductor dice

• US 5,661,901 A
• Filed: 07/10/1995
• Issued: 09/02/1997
• Est. Priority Date: 07/10/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: King, Jerrold L.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US08/499,931
• Time in Patent Office: 785 Days
• Field of Search: 437/226, 437/209, 257/777, 257/687, 257/700, 257/686, 29/830
• US Class Current: 29/830
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/0376 Flush conductors, i.e. flush with the surface of the printed circuit
• CPC Class Codes: H05K 2201/09036 Recesses or grooves in insulating substrate recess in metallic substrate H05K2201/09745
• CPC Class Codes: H05K 3/107 by filling grooves in the support with conductive material H05K3/045, H05K3/101, H05K3/1258 and H05K3/465 take precedence
• CPC Class Codes: H05K 3/146 By vapour deposition
• CPC Class Codes: H05K 3/323 by applying an anisotropic conductive adhesive layer over an array of pads
• CPC Class Codes: H05K 3/366 substantially perpendicularly to each other H05K3/361 takes precedence
• CPC Class Codes: H05K 3/403 Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof H05K3/4092 takes precedence
• CPC Class Codes: Y10T 29/49126 Assembling bases

Abstract

A method for mounting and electrically interconnecting a stack of semiconductor dice on edge to a circuit board is provided. The method forms interconnects adapted to mount each die on edge and establish an electrical connection between contact locations on the die (e.g., bond pads) and corresponding connection points on the circuit board. Each interconnect includes a substrate formed of a material such as silicon or ceramic having a low thermal coefficient of expansion (TCE). Trenches are etched or sawed into the substrate and are then filled with a metal to form conductive traces. Each conductive trace includes contact bump for contacting a contact location on a corresponding die. Z-axis conductive adhesives are used to attach the dice to the interconnects and the interconnects to the circuit board.

Claims

1. A method for mounting an unpackaged semiconductor die to a supporting substrate, said method comprising:

forming an interconnect including a substrate having a plurality conductive traces extending to an edge thereof, each said conductive trace including an insulated trench filled with a conductive material;

attaching a die to the interconnect with contact locations on the die in electrical communication with the conductive traces; and

attaching the interconnect on edge to the supporting substrate with edge portions of the conductive traces in electrical communication with connection points on the supporting substrate.

2. The method as claimed in claim 1 and further comprising forming a plurality of interconnects on a wafer and then singulating the wafer.

3. The method as claimed in claim 2 and wherein the interconnects and dice are attached to the supporting substrate in a stacked array.

4. The method as claimed in claim 3 and wherein the dice are attached to the interconnects using a conductive material.

5. The method as claimed in claim 4 and wherein the interconnects are attached to the supporting substrate using the conductive material.

6. The method as claimed in claim 5 and wherein the wafer is formed of a material selected from the class consisting of silicon and ceramic.

7. The method as claimed in claim 6 and wherein the trenches are formed by etching the wafer.

8. The method as claimed in claim 6 and wherein the trenches are formed by saw cutting the wafer.

9. The method as claimed in claim 6 and wherein the trenches are formed as through openings in the wafer.

10. The method as claimed in claim 6 and wherein the trenches are insulated using a grown oxide layer.

11. A method for attaching an unpackaged semiconductor die to a circuit board, comprising:

forming a wafer including a substrate;

forming a pattern of trenches in the substrate;

forming conductive traces by filling the trenches with a conductive material, each conductive trace having an edge portion extending to a street of the wafer;

forming contact bumps on the conductive traces corresponding to contact locations on the die;

singulating the wafer along the streets thereof to form a plurality of interconnects;

attaching the die to an interconnect with contact locations on the die in electrical communication with the contact bumps on the conductive traces; and

attaching the interconnect on edge to the circuit board with the edge portions of the conductive traces in electrical communication with connection points on the circuit board.

12. The method as claimed in claim 11 and wherein the die is attached to the interconnect using a conductive adhesive.

13. The method as claimed in claim 11 and wherein the interconnect is attached to the circuit board using a conducive adhesive.

14. The method as claimed in claim 11 and wherein the trenches are formed using an etching process.

15. The method as claimed in claim 11 and wherein the trenches are formed by saw cutting.

16. The method as claimed in claim 11 and further comprising forming a channel stop by implanting a dopant around the trenches.

17. The method as claimed in claim 11 and wherein a plurality of dice are attached to a plurality of interconnects attached to the circuit board as a stacked array.

18. A method for attaching a plurality of unpackaged semiconductor dice to a circuit board, comprising:

forming a plurality of interconnects each including a substrate formed of a material selected from the class consisting of silicon and ceramic;

each said substrate including a pattern of conductive traces comprising insulated trenches filled with a conductive material, each said conductive trace extending to an edge of the substrate and including a contact bump corresponding to a contact location on a die;

attaching each die to a respective interconnect with the contact locations of the die in electrical communication with the contact bumps on the conductive traces; and

attaching the interconnects on edge to the circuit board with the conductive traces in electrical communication with connection points on the circuit board to form a stacked array of dice and interconnects.

19. The method as claimed in claim 18 and wherein the conductive traces are formed to be co-planar with a surface of the substrates.

20. The method as claimed in claim 19 and wherein the conductive traces are planarized.

21. The method as claimed in claim 20 and wherein the dice are attached to the interconnects and the interconnects are attached to the circuit board using a z-axis anisotropic adhesive.

22. A method for attaching a plurality of unpackaged semiconductor dice to a circuit board, comprising:

forming a wafer including a substrate having a low thermal coefficient of expansion (TCE);

forming a plurality of interconnects on the wafer each interconnect including a pattern of trenches formed in the substrate and extending to streets formed on the wafer;

forming conductive traces by filling the trenches with a conductive material, each conductive trace including an edge portion corresponding to a connection point on the circuit board;

forming a contact bump on each conductive trace corresponding to a contact location on the die;

sawing the wafer along the streets to singulate the interconnects;

attaching the die to a singulated interconnect with contact locations on the die in electrical communication with the contact bumps formed on the conductive traces; and

attaching the singulated interconnect on edge to the circuit board with the edge portions of the conductive traces in electrical communication with connection points on the circuit board.

23. The method as claimed in claim 22 and wherein the dice are attached to the interconnects and the interconnects are attached to the circuit board using a z-axis anisotropic adhesive.

24. The method as claimed in claim 23 and wherein the conductive traces are planarized.