Semiconductor device package side-by-side stacking and mounting system

• US 5,663,105 A
• Filed: 01/16/1996
• Issued: 09/02/1997
• Est. Priority Date: 05/02/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Yu, Chan Min, Sua, Goh Jing
• Primary Examiner(s): PICARDAT, KEVIN M
• Application Number:
  US08/586,366
• Time in Patent Office: 595 Days
• Field of Search: 257/704, 257/723, 257/724, 257/731, 257/732, 361/729, 361/730, 361/735, 361/744, 361/807, 361/809, 437/51, 437/208, 437/915, 437/209, 437/211, 437/214, 437/215, 437/217, 437/219
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/1005 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2225/1029 the support being a lead frame
• CPC Class Codes: H01L 2225/107 Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
• CPC Class Codes: H01L 2225/1094 Thermal management, e.g. cooling
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 2201/10454 Vertically mounted
• CPC Class Codes: H05K 2201/10537 Attached components
• CPC Class Codes: H05K 2201/10696 Single-in-line [SIL] package
• CPC Class Codes: H05K 3/303 Surface mounted components, e.g. affixing before soldering, aligning means, spacing means H05K3/32 takes precedence
• CPC Class Codes: H05K 3/325 by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor adaptations of leads inserted in holes for press-fit connections H05K3/308
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.

Abstract

The invention is to an array of stacked devices utilizing vertical surface mounted semiconductor devices stacked side by side and inserting the stack of devices into a casing. The packaged stack of devices creates a cube package which is capable of replacing SIMM boards, and saves considerable space. The casing dissipates heat generated in the devices, and may be of metal or thermally conductive plastic.

Claims

1. A method for stacking and mounting a plurality of packaged semiconductor devices on a circuit board, said method comprising:

stacking a plurality of encapsulated vertical surface mount semiconductor device packages side by side within an open bottom cavity of a casing;

said devices packages being stacked vertically into a horizontal array, with front side faces of said packages brought into superposed relationships with rear side faces of adjacent packages, and with bottom edges aligned so that contact leads extending out from respective ones of said bottom edges protrude in a common plane out from said casing open bottom; and

securing said casing to a circuit board to press said contact leads into solderless electrical connection with corresponding contact pads on said board.

2. The method of claim 1, wherein, in said stacking step, said semiconductor device packages are stacked into an array having a top, ends and sides, and said array is positioned within said cavity with said array top, ends and sides in abutment with internal surfaces of corresponding top, ends and sides of said casing.

3. The method of claim 2, wherein said semiconductor device packages have chamfered corners and said cavity has a matching angled edge;

and wherein, in said stacking step, said semiconductor device packages are stacked to align said chamfered corners to form an angled edge in said array, and said array angled edge is positioned in abutting contact with said cavity matching angled edge.

4. The method of claim 3, wherein, in said securing step, said casing is secured to said circuit board by snapping a spring-leaf clip into a hole in said board.

5. A method for mounting multiple packaged semiconductor devices on a circuit board, said method comprising:

providing a plurality of encapsulated vertical surface mount semiconductor device packages, each package having an exterior with front and rear side faces and bottom edges with contact leads extending out from said bottom edges;

positioning said device packages vertically in a side-by-side array with said side faces in adjacent superposed relationships and said bottom edges aligned in a common plane;

enclosing said side-by-side array of semiconductor device packages in a casing, leaving said contact leads exposed; and

securing said casing with said enclosed array onto a circuit board to press said exposed contact leads against said board for establishing solderless electrical connection between said leads and said board.

6. The method according to claim 5, wherein said array has an external contour;

said casing is made from a heat conducting material and has an internal contour that conforms to said external contour of said array; and

said array is enclosed with said internal contour in contact with said external contour.

7. The method according to claim 5, wherein, in said securing step, said casing is releasably secured onto said circuit board.

8. The method according to claim 7, wherein said securing step comprises releasably locking a clip made from a spring-leaf material into a hole on said circuit board.

9. The method according to claim 5, wherein said circuit board is provided with an array of contact pads thereon in positions corresponding to relative positioning of said leads of said semiconductor devices in said array;

and said casing is secured to said circuit board, with said leads respectively pressed against said contact pads.

10. A method for mounting multiple packaged semiconductor devices on a circuit board, each device comprising an integrated circuit chip encapsulated into a discrete protective package and having contact leads extending out of an edge of said package, said method comprising:

positioning said device packages vertically in a side-by-side array;

enclosing said array of semiconductor devices in a casing, leaving said contact leads exposed; and

releasably securing said casing and enclosed semiconductor devices to a circuit board, to press said leads into solderless electrical connection with respective contact pads on said board.

11. The method according to claim 10, wherein said casing is provided with an internal contour that conforms to an external contour of said array of semiconductor device packages;

said casing is made from a heat conducting material; and

said devices are enclosed within said casing with said internal contour in contact with said external contour.

12. The method according to claim 10, wherein said securing step comprises inserting clips on said casing into holes on said circuit board.

13. The method according to claim 12, wherein said securing step comprises releasably locking spring-leaf clips into said holes.

14. The method of claim 11, wherein said semiconductor device packages are provided with chamfered corners;

said chamfered corners are aligned in said array to form an angled external edge;

said casing internal contour is angled to define a corresponding angled internal edge; and

said angled external edge is placed in abutment with said angled internal edge.

15. A method for stacking and mounting multiple packaged semiconductor devices on a circuit board, said method comprising:

providing a plurality of arrays of contact pads on said circuit board;

providing a plurality of casings, each casing having top, end and side walls with internal surfaces defining an internal cavity with an open bottom;

stacking a plurality of encapsulated semiconductor device packages associated with each casing;

said packages each having front and rear side faces, a bottom edge, and contact leads extending from said bottom edge;

stacking the packages of each of said plurality of packages vertically in side-by-side relationships within the respective internal cavity of each associated casing, with said front and rear side faces in superposed relationships and said bottom edges aligned to present said contact leads of the respective packages of each casing in a generally planar array of contact leads exposed at said open bottom; and

securing each casing to said circuit board;

said securing serving to establish solderless electrical contact between leads of said contact lead arrays and respective pads of said contact pad arrays.