High-frequency wireless communication system on a single ultrathin silicon on sapphire chip

• US 5,663,570 A
• Filed: 05/19/1995
• Issued: 09/02/1997
• Est. Priority Date: 07/12/1993
• Status: Expired due to Term

• Current Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Original Assignee: Peregrine Semiconductor Corporation (Murata Manufacturing Co Limited)
• Inventors: Burgener, Mark L., Reedy, Ronald E.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/444,992
• Time in Patent Office: 837 Days
• Field of Search: 257/9, 257/213, 257/280, 257/327, 257/347, 257/350, 257/369, 257/528, 257/531, 257/532, 257/533, 257/536
• US Class Current: 257/9
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02694 Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
• CPC Class Codes: H01L 21/76264 SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
• CPC Class Codes: H01L 21/76281 Lateral isolation by selective oxidation of silicon
• CPC Class Codes: H01L 21/86 the insulating body being sapphire, e.g. silicon on sapphire structure, i.e. SOS
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors
• CPC Class Codes: H01L 29/78657 SOS transistors
• CPC Class Codes: H10B 10/15 comprising a resistor load element
• CPC Class Codes: Y10S 148/15 Silicon on sapphire SOS
• CPC Class Codes: Y10S 438/967 Semiconductor on specified insulator
• CPC Class Codes: Y10S 438/974 Substrate surface preparation
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A high-frequency wireless communication system on a single ultrathin silicon on sapphire chip is presented. This system incorporates analog, digital (logic and memory) and high radio frequency circuits on a single ultrathin silicon on sapphire chip. The devices are fabricated using conventional bulk silicon CMOS processing techniques. Advantages include single chip architecture, superior high frequency performance, low power consumption and cost effective fabrication.

Claims

1. A single chip radio frequency integrated circuit comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

a MOS transistor fabricated in said layer of silicon, said MOS transistor having a gain-bandwidth product of at least 10 GHz; and

a passive component fabricated on said layer of silicon formed on said insulating substrate and connected to said MOS transistor to form an rf circuit, wherein said passive component is selected from the group including a resistor, capacitor and inductor.

2. A single chip radio frequency integrated circuit as defined in claim 1 wherein said insulating substrate comprises sapphire.

3. A single chip radio frequency integrated circuit as defined in claim 1 wherein said layer of silicon has an areal density of electrically active states which is less than approximately 5×

10¹¹ cm^-2.

4. A radio frequency circuit comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

an active circuit portion comprising a MOSFET fabricated in said layer of silicon; and

a passive circuit portion fabricated on an oxidized layer of said layer of silicon formed on said insulating substrate and electrically connected to said active circuit portion to form a radio frequency circuit, wherein said passive circuit portion is selected from the group comprising;

a capacitor;

an inductor; and

a resistor.

5. A wireless communication system comprising:

an insulating substrate;

a layer of silicon formed on said insulating substrate wherein said layer of silicon is less than approximately 1000Å

thick and is substantially free of electrically active states achieved by controlling the temperature of said layer of silicon to temperatures of less than or equal to approximately 950°

C. during any processing of said layer of silicon which exposes said layer of silicon to a non-oxidizing ambient environment;

a radio frequency circuit fabricated in said layer of silicon formed on said insulating substrate wherein said radio frequency circuit includes components selected from the group comprising a switch, an amplifier, a mixer, an oscillator, a phase-locked loop, a filter, a modulator and a demodulator configured as any one of a radio frequency receiver, a radio frequency transmitter or a combination radio frequency transmitter and receiver;

a digital logic and memory circuit fabricated in said layer of silicon formed on said insulating substrate wherein said digital logic and memory circuit includes components selected from the group comprising control circuitry, signal processing circuitry, data storage circuitry and data retrieval circuitry; and

an amplifier circuit fabricated in said layer of silicon formed on said insulating substrate wherein said radio frequency circuit, said digital logic and memory circuit and said amplifier circuit are electrically interconnected.

6. A wireless communication system as defined in claim 5 wherein said insulating substrate comprises sapphire.

7. A wireless communication system as defined in claim 5 wherein said layer of silicon has an areal density of electrically active states which is less than approximately 5×

10¹¹ cm^-2.

8. A radio frequency (RF) electronic circuit capable of operating at a frequency of at least approximately 700 MHz comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment; and

a plurality of radio frequency MOS field effect transistor elements formed in said semiconductive silicon layer wherein said plurality of MOS field effect transistor elements are configured as at least one of a switch, an amplifier, a mixer, an oscillator, a phase-locked loop, a filter, a modulator or a demodulator;

each of said plurality of radio frequency MOS field effect transistor elements further comprising;

a source region formed in said semiconductive silicon layer, wherein a voltage V_S is applied to said source region;

a drain region formed in said semiconductive silicon layer, wherein a voltage V_D is applied to said drain region;

a channel region formed in said semiconductive silicon layer between said source region and said drain region; and

a gate positioned adjacent said channel region with a gate length of less than approximately 0.8 micrometers, wherein a voltage V_G is applied to said gate region to control a current I_DS flowing between said source region and said drain region.

9. A circuit as in claim 8 further comprising at least one passive electronic element selected from the group comprising:

a capacitor;

an inductor; and

a resistor that is connected in circuit with the MOS field effect transistor elements.

10. An integrated circuit comprising:

an electrically insulating substrate;

a semiconductive silicon layer that is formed on the substrate and has a thickness of less than approximately 110 nanometers and an areal density of electrically active states less than approximately 5×

10¹¹ cm^-2 achieved by controlling the temperature of said semiconductive silicon layer to temperatures of less than or equal to approximately 950°

C. during any processing of said semiconductive silicon layer which exposes said semiconductive silicon layer to a non-oxidizing ambient environment;

an analog circuit element which includes at least one radio frequency MOS field effect transistor element that is formed in said semiconductive silicon layer and is capable of operation at a frequency of at least approximately 700 MHz, said radio frequency MOS field effect transistor element further comprising;

a source region formed in said semiconductive silicon layer, wherein a voltage V_S is applied to said source region;

a drain region formed in said semiconductive silicon layer, wherein a voltage V_D is applied to said drain region;

a channel region formed in said semiconductive silicon layer between said source region and said drain region; and

a gate positioned adjacent said channel region, wherein a voltage V_G is applied to said gate region to control a current I_DS flowing between said source region and said drain region;

and

a digital circuit element that is formed in said semiconductive silicon layer and is operatively connected to said analog circuit element, wherein said digital circuit element includes components selected from the group comprising control circuitry, signal processing circuitry, data storage circuitry and data retrieval circuitry.

11. An integrated circuit as in claim 10 in which the analog circuit element and the digital circuit element each comprises a field effect transistor having a gate length of less than approximately 0.8 micrometers.

12. A circuit as in claim 10 further comprising a memory circuit element formed in the semiconductive silicon layer.

13. A circuit as in claim 12 in which the memory circuit element comprises a field effect transistor having a gate length of less than approximately 0.8 micrometers.

14. A circuit as in claim 10 in which the analog circuit element is substantially free of disturbances transmitted through the electrically insulating substrate from the digital circuit element.