Low current redundancy fuse assembly

• US 5,663,658 A
• Filed: 04/12/1996
• Issued: 09/02/1997
• Est. Priority Date: 02/24/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Cowles, Timothy B., Renfro, Steven G.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/631,449
• Time in Patent Office: 508 Days
• Field of Search: 326/38, 326/10, 327/525
• US Class Current: 326/10
• CPC Class Codes: G11C 29/787 using a fuse hierarchy
• CPC Class Codes: G11C 29/83 with reduced power consumption
• CPC Class Codes: G11C 29/832 with disconnection of faulty elements
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence
• CPC Class Codes: H03K 19/1736 in which the wiring can be modified

Abstract

In a microcircuit device such as a memory chip, where a bank of fuse-controlled latch pulse routing-circuits are used to program redundant circuits or other programming options with every memory cycle or multiple thereof, the amount of current drawn by every fuse-control circuit is reduced by controlling each bank of circuits with a bank-enabling, fuse-programmed circuit between the latch pulse source and the bank of fuse-controlled programing circuits, and by adding a second fuse into each programming circuit; whereby, the bank of programming circuits can be enabled by alternately blowing one of two fuses in the bank-enabling circuit, and each programing logic can be set by alternately blowing one of its pair of fuses, thus cutting off any current path through the programming circuit regardless of the programming state of the circuit.

Claims

1. In a microcircuit device having at least one programming logic circuit, said logic circuit including a first programming fuse in series with a switching transistor and a control line connected to a node between said first programming fuse and said switching transistor, a latch pulse source being connected to a control terminal of said switching transistor to generate on said control line a logic level representative of the status of said first programming fuse, an improvement for reducing the current drawn through said first programming fuse comprising:

a second programming fuse connected in series with said first programming fuse between said node and said switching transistor; and

an enabling circuit connected between said latch pulse source and the control terminal of said switching transistor, said enabling circuit comprising;

an enabling transistor having a control terminal connected to said latch pulse source, a first current-carrying terminal connected to a first voltage, and a second current-carrying terminal;

a first enabling fuse having first and second terminals, the first terminal being connected to the enabling transistor'"'"'s second current-carrying terminal and the second terminal being connected to the control terminal of said switching transistor; and

a second enabling fuse having a first terminal connected to the second terminal of said first enabling fuse and a second terminal connected to a second voltage;

whereby programming said first enabling fuse disables said logic circuit, and programming said second enabling fuse allows the passage of a latch pulse through said enabling circuit to said logic circuit.

2. The improvement of claim 1, wherein said first voltage comprises a supply voltage and said second voltage comprises a circuit ground reference.

3. The improvement of claim 1, wherein said logic circuit is connected to an array of microcircuit devices.

4. The improvement of claim 1, wherein said logic circuit is connected to a microcircuit memory array.

5. A method for reducing the amount of current drawn by a bank of programming circuits wherein each circuit includes a current transmitting device mounted in series with a first fuse between a supply voltage and a reference voltage, said method comprising:

adding an extra one of said programming circuits to said bank as a bank-enabling circuit;

in each one of said programming and bank-enabling circuits, adding a second fuse in series between said first fuse and said current transmitting devices;

programming each of said programming and bank-enabling circuits by blowing one of said first and second fuses in each circuit;

driving each of said programming circuits with a signal derived from the junction of said first and second fuses in said bank-enabling circuit; and

using the junction of said first and second fuses in each of said programming circuits as an output indicative of the status of the fuses in said programming circuits.

6. The method of claim 5 further comprising using a transistor as said current transmitting device in said bank-enabling circuit and applying an interrogating signal to a control input of said transistor.

7. A method for reducing the amount of current drawn through a blowable fuse associated with a programming logic circuit, the method comprising:

adding a second fuse in series with said blowable fuse;

setting said programming logic circuit by blowing one of said fuses; and

using a signal at a junction of said fuses as an indication of the status of said fuses.

8. A programmable circuit for outputting a logic signal in a predetermined logic state, the programmable circuit comprising:

a current conduit having a voltage terminal coupled to a first voltage associated with a first logic state and an output terminal for outputting the first voltage; and

a programmable device having an input terminal coupled to the current conduit'"'"'s output terminal, a voltage terminal coupled to a second voltage different than the first voltage and associated with a second logic state, and an output terminal programmably coupleable to the input terminal for outputting the logic signal in the first logic state and to the voltage terminal for outputting the logic signal in the second logic state.

9. The programmable circuit of claim 8 wherein the current conduit comprises a resistance circuit.

10. The programmable circuit of claim 9 wherein the resistance circuit comprises a resistor.

11. The programmable circuit of claim 9 wherein the resistance circuit comprises a resistance-connected transistor.

12. The programmable circuit of claim 8 wherein the current conduit also includes a control terminal for receiving a latch signal from external circuitry and wherein the current conduit'"'"'s output terminal is switchably coupleable to its voltage terminal in response to the latch signal.

13. The programmable circuit of claim 12 wherein the current conduit comprises a control switch.

14. The programmable circuit of claim 13 wherein the control switch comprises a transistor.

15. The programmable circuit of claim 8 wherein one of the first and second voltages is a reference voltage and the other of the first and second voltages is a supply voltage.

16. The programmable circuit of claim 15 wherein the reference voltage is ground.

17. The programmable circuit of claim 8 wherein one of the first and second logic states is a logic "0" state and the other of the first and second logic states is a logic "1" state.

18. The programmable circuit of claim 8 wherein the programmable device comprises first and second programmable elements coupled in series between the current conduit'"'"'s output terminal and the second voltage, the logic signal being output from a node between the programmable elements.

19. The programmable circuit of claim 18 wherein the programmable elements comprise fuses and the output terminal of the programmable device is programmably coupleable to one of the input and voltage terminals of the programmable device by blowing the fuse between the output terminal and the other of the input and voltage terminals.

20. A programmable circuit for outputting a logic signal in a predetermined logic state, the programmable circuit comprising at least two programmable elements and a current conduit coupled in series between a supply voltage and a reference voltage, the supply voltage being associated with a first logic state and the reference voltage being associated with a second logic state, the programmable elements being programmable to alter current flow therethrough such that a node between the programmable elements is programmably coupleable to the supply voltage for outputting the logic signal in the first logic state and to the reference voltage for outputting the logic signal in the second logic state.

21. The programmable circuit of claim 20 wherein the current conduit comprises a resistance circuit.

22. The programmable circuit of claim 20 wherein the current conduit comprises a control switch responsive to a latch signal.

23. The programmable circuit of claim 22 wherein the control switch comprises a transistor.

24. The programmable circuit of claim 20 wherein the programmable elements comprise fuses and the node between the programmable elements is programmably coupleable to one of the supply and reference voltages by blowing the fuse between the node and the other of the supply and reference voltages.

25. A logic circuit for outputting a logic signal in a predetermined logic state in response to a latch signal, the logic circuit comprising:

an enabling circuit comprising an enabling switch and at least two enabling programmable elements coupled in series between a supply voltage and a reference voltage, the supply voltage being associated with a first logic state and the reference voltage being associated with a second logic state, the enabling switch receiving the latch signal and being responsive thereto, the enabling programmable elements being programmable to alter current flow therethrough such that a node between the elements is programmably coupleable to one of the supply and reference voltages for outputting an enabling signal when the latch signal closes the enabling switch; and

a programmable circuit comprising a control switch and at least two output-programmable elements coupled in series between the supply voltage and the reference voltage, the control switch being coupled to the node between the enabling programmable elements for receiving the enabling signal and being responsive thereto, the output programmable elements being programmable to alter current flow therethrough such that a node between the output programmable elements is programmably coupleable to one of the supply and reference voltages for outputting the logic signal in the first or second logic state, respectively, when the enabling signal closes the control switch.

26. The logic circuit of claim 25 wherein the enabling and control switches each comprise a transistor.

27. The logic circuit of claim 25 wherein the programmable elements comprise fuses so each of the nodes between the programmable elements is programmably coupleable to one of the supply and reference voltages by blowing the fuse between the node and the other of the supply and reference voltages.

28. The logic circuit of claim 25 wherein the enabling circuit and the programmable circuit are provided on a single semiconductor.

29. An integrated circuit die comprising:

an enabling transistor and at least two enabling fuses coupled in series between a supply voltage conductor and a reference voltage conductor, the supply voltage being associated with a first logic state and the reference voltage being associated with a second logic state, the enabling transistor being connectable to receive a latch signal from external circuitry and being responsive thereto, the enabling fuses being blowable to alter current flow therethrough such that a node between the fuses is programmably coupleable to one of the supply and reference voltage conductors for outputting an enabling signal when the latch signal rams the enabling transistor on; and

a control transistor and at least two output fuses coupled in series between the supply voltage conductor and the reference voltage conductor, the control transistor being coupled to the node between the enabling fuses for receiving the enabling signal and being responsive thereto, the output fuses being "blowable" to alter current flow therethrough such that a node between the output fuses is programmably coupleable to one of the supply and reference voltage conductors for outputting the logic signal in the first or second logic state, respectively, when the enabling signal closes the control transistor.

30. An integrated circuit package comprising a programmable circuit for outputting a logic signal in a predetermined logic state, the programmable circuit comprising at least two programmable elements and a current conduit coupled in series between a supply voltage conductor and a reference voltage conductor, the supply voltage being associated with a first logic state and the reference voltage being associated with a second logic state, the programmable elements being programmable to alter current flow therethrough such that a node between the programmable elements is programmably coupleable to the supply voltage conductor for outputting the logic signal in the first logic state and to the reference voltage conductor for outputting the logic signal in the second logic state.

31. The integrated circuit package of claim 30 wherein the current conduit comprises a resistance circuit.

32. The integrated circuit package of claim 30 wherein the current conduit comprises a control switch responsive to a latch signal.

33. The integrated circuit package of claim 32 wherein the control switch comprises a transistor.

34. The integrated circuit package of claim 30 wherein the programmable elements comprise fuses so the node between the programmable elements is programmably coupleable to one of the supply and reference voltage conductors by "blowing" the fuse between the node and the other of the supply and reference voltage conductors.

35. A redundant memory system comprising:

a memory array including a plurality of memory cells and a plurality of redundant cells; and

an array accessing circuit coupled to the memory array for selectively accessing memory cells in the memory array in accordance with memory addresses received from external circuitry, the array accessing circuit including a redundancy control circuit comprising;

an enabling circuit including an enabling switch and at least two enabling programmable elements coupled in series between a supply voltage and a reference voltage, the enabling switch receiving a latch signal from external circuitry and being responsive thereto, the enabling programmable elements being programmable to alter current flow therethrough such that a node between the elements is programmably coupleable to one of the supply and reference voltages for outputting an enabling signal when the latch signal closes the enabling switch;

a bank of programmable circuits for storing programmed addresses, each programmable circuit comprising a control switch and at least two output programmable elements coupled in series between the supply voltage and the reference voltage, each control switch being coupled to the node between the enabling programmable elements for receiving the enabling signal and being responsive thereto, each of the output programmable elements being programmable to alter current flow therethrough such that a node between the output programmable elements in each programmable circuit is programmably coupleable to one of the supply and reference voltages for outputting a bit of a programmed address when the enabling signal closes each control switch; and

a latch circuit coupled to the programmable circuits for receiving programmed addresses therefrom, the latch circuit comparing the programmed addresses to received memory addresses and causing the array accessing circuit to selectively access a redundant cell in the memory array in lieu of accessing a memory cell when a received memory address corresponds to a programmed address.

36. The redundant memory system of claim 35 wherein the enabling and control switches comprise transistors.

37. The redundant memory system of claim 35 wherein the programmable elements comprise fuses so each of the nodes between the programmable elements is programmably coupleable to one of the supply and reference voltages by "blowing" the fuse between the node and the other of the supply and reference voltages.

38. A computer system comprising:

an input device;

an output device;

a processor coupled to the input and output devices; and

a memory device coupled to the processor, the memory device including a redundant memory system comprising;

a memory array including a plurality of memory cells and a plurality of redundant cells; and

an array accessing circuit coupled to the memory array for selectively accessing memory cells in the memory array in accordance with memory addresses received from the processor, the array accessing circuit including a redundancy control circuit comprising;

an enabling circuit including an enabling switch and at least two enabling programmable elements coupled in series between a supply voltage and a reference voltage, the enabling switch receiving a latch signal from the processor and being responsive thereto, the enabling programmable elements being programmable to alter current flow therethrough such that a node between the elements is programmably coupleable to one of the supply and reference voltages for outputting an enabling signal when the latch signal closes the enabling switch;

a bank of programmable circuits for storing programmed addresses, each programmable circuit comprising a control switch and at least two output programmable elements coupled in series between the supply voltage and the reference voltage, each control switch being coupled to the node between the enabling programmable elements for receiving the enabling signal and being responsive thereto, each of the output programmable elements being programmable to alter current flow therethrough such that a node between the output programmable elements in each programmable circuit is programmably coupleable to one of the supply and reference voltages for outputting a bit of a programmed address when the enabling signal closes each control switch; and

a latch circuit coupled to the programmable circuits for receiving programmed addresses therefrom, the latch circuit comparing the programmed addresses to received memory addresses and causing the array accessing circuit to selectively access a redundant cell in the memory array in lieu of accessing a memory cell when a received memory address corresponding to the memory cell also corresponds to one of the programmed addresses.

39. A method of programming a memory device having memory cells and redundant cells to generate a programmed address in response to a latch signal for comparison to memory addresses received from external circuitry, the memory device being of the type to access one of its redundant cells in lieu of accessing one of its memory cells when a received memory address matches the programmed address, the method comprising:

providing at least two enabling programmable elements and an enabling switch coupled in series between a supply voltage and a reference voltage, the enabling switch being responsive to the latch signal;

programming the enabling programmable elements to allow conduction of only one of the supply and reference voltages to an enabling node between the elements for outputting an enabling signal therefrom when the latch signal activates the enabling switch;

providing at least two output programmable elements and a control switch coupled in series between the supply and reference voltages for each bit in the programmed address, each control switch being responsive to the enabling signal, the output programmable elements associated with each bit in the programmed address having an output node therebetween for outputting their associated bit; and

programming the output programmable elements associated with each bit in the programmed address to allow conduction of only one of the supply and reference voltages to their associated output node for outputting their associated bit therefrom when the enabling signal activates theft associated control switch, the output nodes thereby generating the programmed address.

40. The programming method of claim 39 wherein the step of programming the enabling programmable elements comprises blowing at least one fuse coupled in series with the enabling switch between the supply and reference voltages and wherein the step of programming the output programmable elements comprises blowing at least one fuse coupled in series with each control switch between the supply and reference voltages.

41. A method in a memory device for accessing a redundant cell of the memory device in lieu of accessing a memory cell of the memory device, the method comprising:

receiving a latch signal and, in response, switchably coupling a first voltage to an enabling node and outputting a corresponding enabling signal therefrom;

activating a control switch associated with each different bit in a programmed address in response to the enabling signal, each control switch being coupled in series with two programmable elements between the first voltage and a second voltage, the second voltage being different than the first voltage, the bit associated with each control switch corresponding to one of the first and second voltages, one programmable element coupled in series with each control switch being preprogrammed to conduct the first or second voltage corresponding to its associated bit through itself, the other programmable element coupled in series with each control switch being preprogrammed to prevent conduction of any voltages through itself;

outputting each different bit in the programmed address from an output node between the programmable elements associated with the bit and thereby outputting the programmed address;

receiving memory addresses corresponding to memory cells in the memory device;

comparing each received memory address to the programmed address; and

when a received memory address and the programmed address correspond, accessing a redundant cell in the memory device in lieu of accessing the memory cell associated with the received memory address.