Controllable variable delay inverter for a process tolerant delay circuit

• US 5,663,670 A
• Filed: 05/08/1996
• Issued: 09/02/1997
• Est. Priority Date: 03/10/1995
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Ueda, Makoto, Iadanza, Joseph Andrew
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TON, MY TRANG
• Application Number:
  US08/646,899
• Time in Patent Office: 482 Days
• Field of Search: 327/264, 327/276, 327/277, 327/278, 327/281, 327/283, 327/284, 327/285, 327/288, 327/309, 327/374, 327/379, 327/389, 327/391, 327/427, 326/23, 326/27
• US Class Current: 327/281
• CPC Class Codes: H03H 11/26 Time-delay networks analogue shift registers G11C27/04
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

A process tolerant delay circuit includes a plurality of inverters that receive an input signal and provide an output signal related to the input signal but including a propagation delay of the plurality of inverters. At least one inverter comprises FETs of minimum channel lengths dependent upon a fabrication process by which the circuit was made. Accordingly, the plurality of inverters have a propagation delay dependent upon the fabrication process. A delay compensation device receives the output signal of the inverters and provides a compensated output signal related to the received signal but including a variable delay established in accordance with a control signal. A process sense stack provides the control signal only during a transition of the input signal, and with a value dependent upon a channel length of a FET device thereof. Thus, the plurality of inverters and delay compensation device operate together, per the control signal of the process sense stack, to provide a circuit capable of compensating for process degradations in order to provide a given delay in accordance with variations in the fabrication process by which they were made.

Claims

1. A variable delay inverter comprising:

input and output nodes;

first and second supply nodes;

a P-FET having its source coupled to said first supply node, its gate coupled to said input node, and its drain coupled to a first internal node;

a first FET having its source/drain coupled to said first internal node, its gate coupled to said second/first supply node so that it is always biased on, and its drain/source coupled to said output node;

a first shunting FET in parallel with said first FET having its source/drain coupled to said source/drain of said first FET, its drain/source coupled to said drain/source of said first FET, and its gate coupled to a control input for receiving a control signal;

an N-FET having its source coupled to said second supply node, its gate coupled to said input node, and its drain coupled to a second internal node;

a second FET having its source/drain coupled to said second internal node;

its gate coupled to said first/second supply node so that it is always biased on, and its drain/source coupled to said output node;

a second shunting FET in parallel with said second FET having its source/drain coupled to said source/drain of said second FET, its drain/source coupled to said drain/source of said second FET, and its gate coupled to said control input for receiving said control signal.

2. A variable delay circuit according to claim 1 wherein said first FET and said second FET have long channel lengths.

3. A variable delay circuit according to claim 2 wherein said first shunting FET and said second shunting FET have short channel lengths.

4. A variable delay circuit according to claim 1 wherein said N-FET, said P-FET, said first FET and said second FET have long channel lengths.

5. A variable delay circuit according to claim 4 wherein said first shunting FET and said second shunting FET have short channel lengths.

6. A variable delay circuit comprising:

input and output nodes;

first and second supply nodes for receiving first and second supply voltages respectively;

a P-PET of a long channel length having its source coupled to said first supply node, and its gate coupled to said input node, and its drain coupled to a first internal node;

a second P-PET of long channel length having its source coupled to said first internal node, its gate coupled to said second supply node so it is always biased on, and its drain coupled to said output node;

a shunting P-FET of short channel length coupled in parallel with said second P-FET having its source coupled to said source of said second P-PET, its drain coupled to said drain of said second P-FET, and its gate coupled to a control input for receiving a control signal;

a first N-FET having its source coupled to said second supply node, its gate coupled to said input node, and its drain coupled to a second internal node;

a second N-FET having its source coupled to said second internal node, its gate coupled to said first supply node so that it is always biased on, and its drain coupled to said output node;

a second shunting P-FET in parallel with said second N-FET having its drain coupled to said source of said second N-FET, its source coupled to said drain of said second N-FET, and its gate coupled to said control input for receiving said control signal.