Single-buffer data formatter for spatial light modulator

• US 5,663,749 A
• Filed: 03/21/1995
• Issued: 09/02/1997
• Est. Priority Date: 03/21/1995
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Farris, Jeffrey S., Kalthoff, Stephen G.
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US08/407,569
• Time in Patent Office: 896 Days
• Field of Search: 345/84, 345/189, 345/190, 345/200, 395/425, 348/716, 348/718, 348/441, 348/771, 348/573, 348/743, 365/230.02, 365/189.02, 365/230.05
• US Class Current: 348/771
• CPC Class Codes: G09G 2310/0235 Field-sequential colour display
• CPC Class Codes: G09G 3/2022 using sub-frames
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/34 by control of light from an independent source
• CPC Class Codes: G09G 3/346 based on modulation of the reflection angle, e.g. micromirrors micromirrors devices per se G02B26/0833
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: H04N 9/30 using solid-state colour display devices

Abstract

A formatter (13) for formatting data for use by a spatial light modulator (15) in an image display system (10). The formatter (13) converts data from pixel format to bit-plane format. The formatter (13) has a square array of memory cells (41), which are connected so that they can shift data either across the array from column to column (vertically) or down the array from row to row (horizontally). The loading of data to the array is toggled between vertical and horizontal loading (FIGS. 6A-6D). While the array is loaded vertically from one side, data is shifted out of the array at the other side. While the array is loaded horizontally from the top, data is shifted out at the bottom. Because of the orthogonal input versus output, the output data is arranged by bit-weight rather than by pixel.

Claims

1. A data formatter for a spatial light modulator having individually addressable pixels for generating images based on pixel data, comprising:

a square array of memory cells, each memory cell for storing a bit of pixel data, wherein said square array has a size corresponding to a data size of n pixels each having an n-bit value;

a vertical input line and a horizontal input line connected to an input of each memory cell;

a multiplexer at said input of each memory cell for determining whether said bit shall be written to said memory cell from said vertical input line or from said horizontal input line;

a vertical output line and a horizontal output line connected to an output of each memory cell; and

a multiplexer at said output of each memory cell for determining whether said bit shall be read from said memory cell to said vertical output line or to said horizontal output line.

2. The data formatter of claim 1, wherein said memory cells are flip flops.

3. The data formatter of claim 1, wherein said square array has a size corresponding to a data size of n pixels each having an n-bit value.

4. A method of converting data from pixel format to bit-plane format, comprising the steps of:

vertically loading a square array of memory cells with data, via vertical input lines connected to a first column of said memory cells, said loading being accomplished by shifting said data column by column into said square array;

outputting columns of data via vertical output lines connected to a last column of said memory cells, during said vertically loading step;

horizontally loading said square array of memory cells with data, via horizontal input lines connected to a first row of said memory cells, said loading being accomplished by shifting said data row by row down said array;

outputting rows of data from a last row of said memory cells, during said horizontally loading step; and

alternating between said vertically loading step and said horizontally loading step.

5. The method of claim 4, wherein said loading steps are performed by loading n pixels having n-bit values.

6. The method of claim 4, wherein said loading steps are performed by switching between said vertical input lines and said horizontal input lines.

7. The method of claim 4, wherein said switching is performed with multiplexers on a pair of input lines associated with each memory cell.

8. The method of claim 4, wherein said switching is performed with a tristate driver on each input line.

9. The method of claim 4, wherein said outputting step is performed by switching between said vertical output lines and said horizontal output lines.

10. The method of claim 4, wherein said switching is performed with multiplexers on a pair of output lines associated with each memory cell.

11. The method of claim 4, wherein said switching is performed with a tristate driver on each output line.