Apparatus for computing delay time of integrated circuit

• US 5,663,889 A
• Filed: 12/07/1994
• Issued: 09/02/1997
• Est. Priority Date: 12/28/1993
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited, Fujitsu VLSI Limited (Fujitsu Limited)
• Inventors: Wakita, Makoto
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): GARBOWSKI, LEIGH M
• Application Number:
  US08/351,646
• Time in Patent Office: 1,000 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491, 364/578
• US Class Current: 716/108
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A delay time computing apparatus includes a data base for storing data on various cells, an input device operable by a designer, and a processing unit coupled to the data base and the input device. The processing unit includes a data input interface, a path building section and a delay time computing section. The data input interface controls transfer of input data from the input device. The path building section reads detailed data on a selected cell from the data base in accordance with circuit redesign data input by a circuit designer to the data input device, and thereby constructs a signal propagation path for cells involved in circuit redesign. Every time the path building section constructs new signal propagation paths, the delay time computing section computes delay times of cells involved in circuit redesign.

Claims

1. An apparatus for computing delay times of integrated circuits, comprising:

a data base storing data on various cells to be used in designing integrated circuits;

input unit operable by a designer to redesign a circuit under design; and

a processing unit coupled to said data base and said input means, said processing unit including;

a data input interface, coupled to said input unit, controlling the transfer of input data from said input unit,

a signal path building section, coupled to said data input interface, receiving circuit design data input by the designer on a redesigned circuit, and reconstructing a new signal propagation path coupling a cell affected by the redesign of circuit by referring to the data input by the designer, and

a signal delay time computing section, coupled to said signal path building section, computing a signal delay time for the cells coupled along the new signal propagation path while reconstructing the new signal propagation path.

2. The apparatus according to claim 1 further comprising an output unit showing delay times computed by said processing unit, and

wherein said processing unit further includes an output data preparing section, coupled to said output unit, displaying both the path constructed by said signal path building section and a delay time computed by said signal delay time computing section on said output unit.

3. The apparatus according to claim 2, wherein said output unit includes at least one of a CRT and a printer.

4. The apparatus according to claim 1, wherein said input unit includes at least one selected from the group consisting of a card reader, a keyboard and a mouse interface.

5. The apparatus according to claim 1, wherein the cell data, stored in said data base, includes a total delay time computation equation and parameters corresponding to the propagation delay of an input signal to a cell;

and

wherein at the time of computing the delay time of a cell involved in circuit redesign, said delay time computing section uses the propagation delay value determined at the output of a cell preceding the redesigned cell as the propagation delay value at the input of the redesigned cell, and computes the delay time of the redesigned cell based on said total delay time computation equation and parameters.

6. The apparatus according to claim 1, wherein the cell data, stored in said data base, includes a total delay time computation equation and parameters reflective of circuit parameters at terminals other than at the terminal of a redesigned cell coupled to said reconstructed path;

and

wherein at the time of computing the delay time of a cell involved in circuit redesign, said delay time computing section computes the delay time of the redesigned cell based on said total delay time computation equation and parameters.

7. A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit, said method comprising the steps of:

inputting data about the redesign of a circuit cell as an element of a circuit;

constructing a, new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer;

computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation paths, every time the new path is constructed.

8. A method of computing delay times of signals used in integrated circuits using a computer aided design system including a data base, input unit and processing unit having a delay time computing section, said method comprising the steps of:

inputting data about the redesign of a circuit cell as an element of a circuit;

constructing a new signal propagation path for the redesigned circuit cell by referring to the data input to said input unit by a circuit designer; and

computing a delay time of the cell affected by the circuit redesign and included in the new signal propagation path, every time the new path is constructed,

wherein the cell data, stored in said data base, includes a total delay time computation equation and parameters corresponding to the propagation delay of an input signal to a cell, and

wherein at the time of computing the delay time of the cell involved in circuit redesign, said delay time computing section uses the propagation delay value determined at the output of a cell preceding the redesigned cell as the propagation delay value at the input of the redesigned cell, and computes the delay time of the redesigned cell based on said total delay time computation equation and parameters.