Electronic simulation and emulation system

• US 5,663,900 A
• Filed: 05/09/1995
• Issued: 09/02/1997
• Est. Priority Date: 09/10/1993
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.), Vanguard Systems Incorporated (MHC Software LLC)
• Original Assignee: Vasona Systems, Inc.
• Inventors: Bhandari, Narpat, Watkins, Daniel R.
• Primary Examiner(s): Ramirez, Ellis B.
• Application Number:
  US08/437,957
• Time in Patent Office: 847 Days
• Field of Search: 364/578, 364/579
• US Class Current: 716/106
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

In an electronic design automation (EDA) system, various models are simulated and interfaced to certain target systems, logic analyzers, modeler, functional testers, emulators, hardware accelerators, hardware modelers, or other simulators. An add-on circuit card connects the simulator to the external systems. A computer program controls simulation start, stop, single-stepping, polling, interrupting and signal monitoring. The software program includes a model input/ouput file, a model input/output parcer, a configuration module, an address generation module, a run-time module, and a C-language module.

Claims

1. An electronic verification system comprising:

an external system;

a bus circuit having a first port coupled to said external system for transferring data between said bus circuit and said external system and a second port; and

a first simulation module coupled to said second port of said bus circuit for simulating and verifying a prototype definition of said external system.

2. The electronic verification system of claim 1 wherein said bus circuit includes an interface circuit for interfacing data transfer between said external system and said first simulation module.

3. The electronic verification system of claim 1 further comprising a circuit pod with two parts, the first part containing an adapter with a plurality of socket pins connected to said external system and the second part connected to said interface card.

4. The electronic verification system of claim 1 wherein the prototype definition comprises a plurality of simulation models, wherein at least one of the simulation models comprises a first-level simulation model, and at least one of the simulation models comprises a second-level simulation model.

5. The electronic verification system of claim 1 wherein the prototype definition comprises at least one simulation model.

6. The electronic verification system of claim 5 wherein each simulation model is defined according to a specified configuration.

7. The electronic verification system of claim 6 wherein data are transferred during simulation between the prototype definition and each external system according to a specified file format.

8. The electronic verification system of claim 5 wherein at least one of the simulation models comprises an analog component model, and at least one of the simulation models comprises a digital component model.

9. The electronic verification system of claim 5 wherein at least one of the simulation models comprises a memory component model.

10. The electronic verification system of claim 5 wherein each simulation model comprises at least one configurable signal path definition.

11. The electronic verification system of claim 1 wherein the simulation module is coupled to a hardware simulation accelerator.

12. The electronic verification system of claim 1 wherein the simulation module is coupled to a hardware modeler.

13. An electronic verification system comprising:

an external system containing a socket for connection with a prototype system;

a bus circuit having a first port coupled to said external system for transferring data between said bus circuit and said external system, and having a second port, said bus circuit includes an interface circuit;

a first simulation module coupled to said second port of said interface circuit for simulating and verifying a prototype definition of said external system.

14. The electronic verification system of claim 13 wherein said prototype system includes a prototype semiconductor device.

15. The electronic verification system of claim 13 wherein said prototype system includes a connector for plugging-in a system.

16. The electronic verification system of claim 13 wherein said interface circuit further comprises:

a buffer for sending data to an input/output pin of said external system;

a first register with an input connected to the input/output pin of said external system and an output connected to said tool;

a second register with an input from said tool and an output to said buffer for enabling or disabling the transfer function of said buffer;

a third register with an input from said tool and an output connected to said buffer for transferring data to said buffer.

17. The electronic verification system of claim 13 wherein the external system comprises a second simulation module for simulating a second prototype definition.

18. The electronic verification system of claim 17 wherein the second simulation module is synchronized with the tool, such that the second prototype definition cooperates functionally with the prototype definition.

19. The electronic verification system of claim 18 wherein a third simulation module is coupled to the tool, wherein the third simulation module cooperates functionally with the second simulation module through the tool.

20. The electronic verification system of claim 17 wherein the second simulation module functionally cooperates with the first simulation module wherein the first simulation module causes a logic state to be set in the second prototype definition.

21. The electronic verification system of claim 17 wherein the external system comprises a hardware emulator.

22. The electronic verification system of claim 17 wherein the external system comprises a hardware modeler.

23. The electronic verification system of claim 17 wherein the external system comprises a hardware simulation accelerator.

24. The electronic verification system of claim 13 wherein the external system comprises a logic analyzer.

25. The electronic verification system of claim 13 wherein the external system comprises a functional tester.

26. The electronic verification system of claim 13 wherein the simulation module and each external system are implemented separately on different processors.

27. The electronic verification system of claim 13 wherein the simulation module and at least one external system are implemented on a single processor.

28. The electronic verification system of claim 13 wherein the simulation module and at least one external system are implemented in a set of processors.

29. The electronic verification system of claim 13 wherein the functional cooperation between the simulated prototype definition and each external system is substantially asynchronous.

30. The electronic verification system of claim 13 wherein a plurality of test signals are obtained from the first simulation module during simulation.

31. The electronic verification system of claim 13 wherein the first simulation module is implemented on a processor, and the interface comprises additional circuitry coupled to the processor.

32. The electronic verification system of claim 31 wherein the additional circuitry comprises a card coupled to each external system.

33. The electronic verification system of claim 32 wherein the card is coupled to a connector which is coupled to at least one socket in at least one of the external systems.

34. The electronic verification system of claim 32 wherein the card provides a signal path between at least one specified signal pin in each coupled socket to at least one specified signal pin in the simulated prototype definition.

35. The electronic verification system of claim 34 wherein the card connects a first conduction point in at least one external system to a second conduction point in the simulated prototype definition.

36. The electronic verification system of claim 35 wherein the connection comprises a bi-directional signal path.

37. The electronic verification system of claim 35 wherein the connection comprises a digital-to-analog converter (DAC) or analog-to-digital converter (ADC) circuit.

38. The electronic verification system of claim 35 wherein the connection enables inter-system signal communication, without user intervention to set-up interface parameters.

39. The electronic verification system of claim 34 wherein a signal path delay is determined for the signal path.

40. The electronic verification system of claim 39 wherein a timing parameter of one of the external systems is adjusted in response to the signal path delay.

41. The electronic verification system of claim 13 further comprising a software program for controlling the tool.

42. The electronic verification system of claim 41 wherein the software program causes the first simulation module to begin simulation.

43. The electronic verification system of claim 42 wherein the software program causes the first simulation module to stop simulation.

44. The electronic verification system of claim 43 wherein the software program causes the first simulation module simulation to be monitored.

45. The electronic verification system of claim 43 wherein type software program causes the first simulation module to single-step simulation.

46. The electronic verification system of claim 43 wherein the software program causes the first simulation module to modify a simulation process.

47. The electronic verification system of claim 46 wherein the modification comprises an interruption of the simulation process.

48. The electronic verification system of claim 46 wherein the modification comprises a polling of the simulation process.

49. The electronic verification system of claim 43 wherein the software program comprises a model input/output file which is generated from specified signal information provided in the prototype definition.

50. The electronic verification system of claim 49 wherein the software program further comprises a model input/output parcer which evaluates and formats the specified signal information.

51. The electronic verification system of claim 50 wherein the software program further comprises a configuration module which maps the formatted signal information into corresponding model representations.

52. The electronic verification system of claim 41 wherein the software program further comprises an address generation module including specified addresses for configuring the interface.

53. The electronic verification system of claim 42 wherein the software program further comprises a run-time module for module coordination.

54. The electronic verification system of claim 43 wherein the software program further comprises a routine module including specified routines which are usable by the run-time module for functional cooperation with the tool.

55. The electronic verification system of claim 13 wherein the first simulation module and the interface are assembled for stand-alone operation such that the assembly is substantially portable.

56. The electronic verification system of claim 13 wherein the first simulation module and the interface are assembled for embedded operation in one of the external systems such that the assembly is substantially dedicated for embedded operation.

57. The electronic verification system of claim 13 wherein the prototype definition is implemented in reconfigurable hardware logic.

58. The electronic verification system of claim 13 wherein the first simulation module is reconfigured for simulating a revised prototype definition, wherein the interface provides distributable access by the reconfigured first simulation module to at least one external system, thereby enabling functional cooperation between the revised prototype definition and each accessed external system.

59. An electronic verification system comprising:

a simulation module for simulating a prototype definition comprising a plurality of simulation models, wherein each simulation model is defined according to a specified configuration, at least one of the simulation models comprising a first-level simulation model, at least one of the simulation models comprising a second-level simulation model, each simulation model comprising at least one configurable signal path definition; and

an interface coupled to the tool;

wherein the interface provides distributable access by the simulation module to at least one external system, functional cooperation being enabled between the simulated prototype definition and each external system, and data are transferred during simulation between the prototype definition and each external system according to a specified file format.

60. The electronic verification system of claim 59 wherein one of the external systems comprises a second simulation module for simulating a second prototype definition, the second simulation module being synchronized with the tool, such that the second prototype definition functionally cooperates with the prototype definition.

61. The electronic verification system of claim 60 wherein the simulation module is implemented on a processor, and the interface comprises additional circuitry coupled to the processor, the additional circuitry comprising a card coupled to each external system, the card being coupled to a connector which is coupled to at least one socket in at least one of the external systems, the card providing a signal path between at least one specified conduction point in each coupled socket to at least one specified conduction point in the simulated prototype definition.

62. The electronic verification system of claim 60 further comprising a software program for controlling the tool, the software program causing the simulation module to begin, monitor, interrupt, poll or stop simulation, the software program comprising a model input/output file which is generated from specified signal information provided in the prototype definition, a model input/output parcer which evaluates and formats the specified signal information, a configuration module which maps the formatted signal information into corresponding model representations, an address generation module including specified addresses for configuring the interface, a run-time module for module coordination, and a routine module including specified routines which are usable by the run-time module for functional cooperation with the tool.