Interleaving architecture and method for a high density FIFO

• US 5,663,910 A
• Filed: 12/29/1995
• Issued: 09/02/1997
• Est. Priority Date: 07/22/1994
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Au, Fu Lam, Ko, Ray-Jane, Chiang, Joseph P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/581,703
• Time in Patent Office: 613 Days
• Field of Search: 365/189.04, 365/189.05
• US Class Current: 365/189.05
• CPC Class Codes: G06F 2205/062 Allowing rewriting or rereading data to or from the buffer
• CPC Class Codes: G06F 5/14 for overflow or underflow handling, e.g. full or empty flags
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

A plurality of parallel single port memory arrays are coupled between a corresponding plurality of input FIFO sets and a corresponding plurality of output FIFO sets to create a high-speed FIFO memory device. The input FIFO sets, which provide data values to their corresponding single port memory arrays, are responsive to a write clock signal. The output FIFO sets, which receive data values from their corresponding single port memory arrays, are responsive to a read clock signal. The order of read and write operations within each single port memory array is controlled by a corresponding state machine which is coupled to either the write clock signal or the read clock signal. Each of the parallel single port memory arrays operates independently. The input FIFO sets de-interleave an input data stream into a plurality of intermediate data streams. Each intermediate data stream is routed through a single port memory array to an output FIFO set. The intermediate data streams are interleaved and transmitted to an output port. In one embodiment, the high-speed FIFO memory device has the capability to retransmit previously transmitted information.

Claims

1. A method for retransmitting data values from a synchronous first in, first out (FIFO) memory device having an input port coupled to provide data values to an input FIFO, a single port memory coupled to receive data values from said input FIFO, an output FIFO coupled to receive data values from said single port memory, and an output port coupled to receive data values from said output FIFO, said method comprising the steps of:

preventing data values from being written to said input FIFO for a first predetermined time period;

preventing data values from being read from said output port for said first predetermined time period;

resetting a read address counter associated with said single port memory to an address representative of an initial address position within said single port memory;

clearing said output FIFO; and

then

sequentially reading data values from said single port memory to said output FIFO beginning at said initial address position of said single port memory; and

allowing data values to be read from said output port.

2. The method of claim 1, further comprising the step of initiating the method in response to a first retransmit signal.

3. The method of claim 2, further comprising the step of preventing said FIFO memory device from operating in response to a second retransmit signal for a second predetermined period after the first retransmit signal is received.

4. The method of claim 1, further comprising the step of, reading data values stored in said input FIFO to said single port memory during said first predetermined time period.

5. The method of claim 1, further comprising the step of initializing a state machine which controls said single port memory before the step of sequentially reading data values from said single port memory.

6. The method of claim 5, further comprising the steps of:

resetting a write counter associated with the output FIFO; and

resetting a read counter associated with the input FIFO.

7. The method of claim 5, further comprising the step of setting a signal to indicate that said output FIFO is empty.

8. The method of claim 5, further comprising the step of setting a signal to indicate that said single port memory is empty.

9. The method of claim 5, further comprising the step of allowing data values to be written to said input port after the step of sequentially reading data values from said single port memory.