Semiconductor circuit having MOS circuit for use in strong electric field

• US 5,663,917 A
• Filed: 08/03/1995
• Issued: 09/02/1997
• Est. Priority Date: 11/15/1994
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Yanagisawa, Makoto, Fujii, Yasuhiro, Mochizuki, Hirohiko, Oka, Tomoharu
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/510,862
• Time in Patent Office: 761 Days
• Field of Search: 365/226, 365/230.06, 365/230.08, 365/185.23, 327/530
• US Class Current: 365/226
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H03K 17/08122 in field-effect transistor switches
• CPC Class Codes: H03K 17/102 in field-effect transistor switches

Abstract

A semiconductor circuit has a first transistor, a second transistor, a third transistor, and a fourth transistor. The first and fourth transistors are a first conduction type, and the second and third transistors are a second conduction type opposite to the first conduction type. The semiconductor circuit employs a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside of the range determined by the first voltage and the second voltage. The first, second, and third transistors are connected in series between the second power supply line and the third power supply line, and the fourth transistor is connected between an input terminal and a control electrode of the first transistor.

Claims

1. A semiconductor circuit employing a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside a range determined by said first voltage and said second voltage, wherein said semiconductor circuit comprises:

a first transistor of a first conduction type;

a second transistor of a second conduction type opposite to said first conduction type;

a third transistor of said second conduction type, said first, second, and third transistors being connected in series between said second power supply line and said third power supply line;

a fourth transistor of said first conduction type, connected between an input terminal and a control electrode of said first transistor.

2. A semiconductor circuit as claimed in claim 1, wherein said semiconductor circuit further comprises a fifth transistor of said second conduction type, connected between said input terminal and a control electrode of said second transistor.

3. A semiconductor circuit as claimed in claim 2, wherein the voltage of said first power supply line is applied to control electrodes of said third and fifth transistors.

4. A semiconductor circuit as claimed in claim 1, wherein said semiconductor circuit further comprises a sixth transistor of said first conduction type, connected between said first transistor and said third transistor, and a specific voltage is applied to the control electrodes of said fourth and sixth transistors.

5. A semiconductor circuit as claimed in claim 4, wherein said specific voltage applied to the control electrodes of said fourth and sixth transistors is determined to be a voltage lower than twice the threshold voltage of said fourth transistor.

6. A semiconductor circuit as claimed in claim 1, wherein each transistor of said first conduction type is determined to be a P-channel type MOS transistor, and each transistor of said second conduction type is determined to be an N-channel type MOS transistor.

7. A semiconductor circuit as claimed in claim 1, wherein said semiconductor circuit is applied to a pre-word decoder of a semiconductor memory, and word lines of said semiconductor memory are controlled by said semiconductor circuit.

8. A semiconductor circuit as claimed in claim 1, wherein said first voltage is a normal high power supply voltage, said second voltage is a low power supply voltage, and said third voltage is a super high power supply voltage higher than said normal high power supply voltage.

9. A semiconductor circuit employing a first power supply voltage, a second power supply voltage, and a third power supply voltage outside a range determined by said first power supply voltage and second power supply voltage, wherein said semiconductor circuit comprises:

a first transistor of a first conduction type, and a strong electric field caused by said second power supply voltage and said third power supply voltage being applied to said first transistor; and

a second transistor of said first conduction type, said second transistor being inserted between an input terminal and a control electrode of said first transistor, and a control electrode of said second transistor being set at a voltage determined by subtracting twice the threshold voltage of said first and second transistors from said first power supply voltage or set at a voltage lower than the determined voltage.

10. A semiconductor circuit as claimed in claim 9, wherein said first and second transistors of said first conduction type are determined to P-channel type MOS transistors.

11. A semiconductor circuit as claimed in claim 9, wherein said semiconductor circuit further comprises:

a third transistor of a second conduction type opposite to said first conduction type, and a strong electric field caused by said second power supply voltage and said third power supply voltage being applied to said third transistor; and

a fourth transistor of said second conduction type, said fourth transistor being inserted between an input terminal and a control electrode of said third transistor, and a control electrode of said fourth transistor being set at said first power supply voltage or lower.

12. A semiconductor circuit as claimed in claim 11, wherein said third and fourth transistors of said second conduction type are determined to be N-channel type MOS transistors.

13. A semiconductor circuit as claimed in claim 9, wherein said semiconductor circuit is applied to a pre-word decoder of a semiconductor memory, and word lines of said semiconductor memory are controlled by said semiconductor circuit.

14. A semiconductor circuit as claimed in claim 9, wherein said first power supply voltage is a normal high power supply voltage, said second power supply voltage is a low power supply voltage, and said third power supply voltage is a super high power supply voltage higher than said normal high power supply voltage.

15. A semiconductor memory having a plurality of word lines, a plurality of bit lines, a plurality of memory cells each positioned at an intersection portion between a word line and a bit line, a column decoder for selecting a bit line, a word decoder for selecting a word line, and a pre-word decoder receiving address signals and controlling said word decoder, said pre-word decoder employing a first power supply line for supplying a first voltage, a second power supply line for supplying a second voltage, and a third power supply line for supplying a third voltage outside a range determined by said first voltage and said second voltage, wherein said pre-word decoder comprises:

a first transistor of a first conduction type;

a second transistor of a second conduction type opposite to said first conduction type;

a third transistor of said second conduction type, said first, second, and third transistors being connected in series between said second power supply line and said third power supply line;

a fourth transistor of said first conduction type, connected between an input terminal and a control electrode of said first transistor.

16. A semiconductor memory as claimed in claim 15, wherein said pre-word decoder further comprises a fifth transistor of said second conduction type, connected between said input terminal and a control electrode of said second transistor.

17. A semiconductor memory as claimed in claim 16, wherein a voltage of said first power supply line is applied to control electrodes of said third and fifth transistors.

18. A semiconductor memory as claimed in claim 15, wherein said pre-word decoder further comprises a sixth transistor of said first conduction type, connected between said first transistor and said third transistor, and a specific voltage is applied to the control electrodes of said fourth and sixth transistors.

19. A semiconductor memory as claimed in claim 18, wherein said specific voltage applied to the control electrodes of said fourth and sixth transistors is determined to be a voltage lower than twice the threshold voltage of said fourth transistor.

20. A semiconductor memory as claimed in claim 15, wherein each transistor of said first conduction type is determined to be a P-channel type MOS transistor, and each transistor of said second conduction type is determined to be an N-channel type MOS transistor.

21. A semiconductor memory as claimed in claim 15, wherein said first voltage is a normal high power supply voltage, said second voltage is a low power supply voltage, and said third voltage is a super high power supply voltage higher than said normal high power supply voltage.

22. A semiconductor memory having a pre-word decoder employing a first power supply voltage, a second power supply voltage, and a third power supply voltage outside a range determined by said first power supply voltage second power supply voltage, wherein said pre-word decoder comprises:

a first transistor of a first conduction type, a strong electric field caused by said second power supply voltage and said third power supply voltage being applied to said first transistor; and

a second transistor of said first conduction type, said second transistor being inserted between an input terminal and a control electrode of said first transistor, and a control electrode of said second transistor being set at a voltage determined by subtracting twice the threshold voltage of said first and second transistors for said first power supply voltage or set at a voltage lower than the determined voltage.

23. A semiconductor memory as claimed in claim 22, wherein said first and second transistors of said first conduction type are determined to be P-channel type MOS transistors.

24. A semiconductor memory as claimed in claim 22, wherein said pre-word decoder further comprises:

a third transistor of a second conduction type opposite to said first conduction type, and a strong electric field caused by said second power supply voltage and said third power supply voltage being applied to said third transistor; and

a fourth transistor of said second conduction type, said fourth transistor being inserted between an input terminal and a control electrode of said third transistor, and a control electrode of said fourth transistor being set at said first power supply voltage.

25. A semiconductor memory as claimed in claim 24, wherein said third and fourth transistors of said second conduction type are determined to be N-channel type MOS transistors.

26. A semiconductor memory as claimed in claim 22, wherein said first power supply voltage is a normal high power supply voltage, said second power supply voltage is a low power supply voltage, and said third power supply voltage is a super high power supply voltage higher than said normal high power supply voltage.