Communication data receiver capable of minimizing the discarding of received data during an overflow

• US 5,663,948 A
• Filed: 06/01/1995
• Issued: 09/02/1997
• Est. Priority Date: 06/01/1994
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Kobunaya, Hideki
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/456,691
• Time in Patent Office: 824 Days
• Field of Search: 370/60, 370/60.1, 370/61, 370/94.1, 370/94.2, 370/100.1, 370/103, 370/105.1, 370/105.4, 370/106, 370/112, 370/113, 370/47, 370/48, 370/99, 370/108, 375/365, 375/360, 375/361, 375/370, 375/372, 395/849, 395/119, 395/856, 395/115.2, 395/827, 395/307, 395/877, 395/182.08, 395/881, 395/800, 371/5.4, 365/14.9, 365/230.06, 365/228.3, 365/231.9, 365/232.8
• US Class Current: 370/229
• CPC Class Codes: H04L 2012/5616 Terminal equipment, e.g. codecs, synch.
• CPC Class Codes: H04L 2012/563 Signalling, e.g. protocols, reference model
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A communication data receiver comprises a counter for generating a write address on a buffer memory for communication cell data according to a write signal directing the communication cell data to be written into the buffer memory, a latch circuit for holding a write address for start communication cell data being written, an overflow detection circuit for detecting an overflow of the buffer memory, a circuit for prohibiting communication cell data from being written into the buffer memory according to an overflow detection signal, and a circuit for setting a write address held in the latch circuit as a writing start address for the next received communication cell data in the counter according to the overflow detection signal.

Claims

1. A communication data receiver for storing communication cell data received from a communication layer into a buffer memory and transferring said communication cell data to another communication layer, said communication data receiver comprising:

a cell synchronous means for generating a synchronizing signal and a start detection signal when said received communication cell data is synchronized and a start of said received communication cell data has been detected;

a write signal generation means for generating a write signal that directs said communication cell data to be written into said buffer memory according to said synchronizing signal and said start detection signal;

a means for holding a write address of a start data of said communication cell data being written;

a means for detecting an overflow of said buffer memory;

a means for inactivating said write signal according to an overflow detection signal output by said overflow detection means; and

a means for setting the write address held in said write address holding means as a writing start address for said communication cell data received next according to said overflow detection signal.

2. A communication data receiver as set forth in claim 1, which further comprises:

a write address generation means for generating the write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means; and

a means for setting the write address held in said write address holding means at said write address generation means as the writing start address for said communication cell data received next according to said overflow detection.

3. A communication data receiver as set forth in claim 1, which further comprises:

a write address generation means for generating the write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means;

wherein said write address holding means includes a latch circuit for holding the write address of the start data of said communication cell data output from said write address generation means according to the start detection signal of said communication cell data delayed by one clock period;

said write address generation means loading said write address held in said latch circuit according to said overflow detection signal.

4. A communication data receiver as set forth in claim 3, which further comprises:

a flip flop for receiving the start detection signal of said communication cell data and outputting said start detection signal delayed by one clock period;

wherein said latch circuit holds the write address for the start data of said communication cell data output from said write address generation means by said start detection signal delayed by one clock output from said flip flop.

5. A communication data receiver as set forth in claim 1, which further comprises:

a write address generation means for generating the write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means; and

a read address generation means for generating a read address for use in reading data from said buffer memory;

said overflow detection means including;

an address judgment means for judging whether a value of said write address is identical to value of said read address;

a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;

a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;

a comparison means for comparing said first flag with said second flag; and

a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that an address coincidence signal output from said address judgment means is not identical to said first and second flags from said comparison means.

6. A communication data receiver as set forth in claim 1, which further comprises:

a write address generation means for generating a write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means; and

a read address generation means for generating a read address for use in reading data from said buffer memory;

said overflow detection means including;

a subtraction means for calculating the difference between said write address and said read address;

a zero detection means for judging whether the value calculated by said subtraction means is zero;

a first flag for inverting a value every time said write address checks a set of addresses of said buffer memory;

a second flag for inverting a value every time said read address checks a set of addresses of said buffer memory;

a comparison means for comparing said first flag with said second flag; and

a means for outputting an overflow signal indicating an overflow of said buffer memory by entering a signal signifying that a zero detection signal output from said zero detection means is not identical to said first and second flags output from said comparison means.

7. A communication data receiver as set forth in claim 1, wherein

said write signal generation means is set by a logical product of said synchronizing signal and said start detection signal and includes a flip flop for outputting the write signal for said buffer memory;

said flip flop is reset by said overflow detection signal output from said overflow detection means to activate said write signal.

8. A communication data receiver for storing communication cell data received from a communication layer into a buffer memory and transferring said communication cell data to another communication layer, said communication data receiver comprising:

a cell synchronous means for generating a synchronizing signal and a start detection signal when said received communication cell data is synchronized and a start of said received communication cell data has been detected;

a write signal generation means for generating a write signal directing said communication cell data to be written into said buffer memory according to said synchronizing signal and said start detection signal;

an upper address generation means for generating certain upper bits of a write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means;

a lower address generation means for generating certain lower bits of the write address on said buffer memory for said communication cell data according to said write signal output from said write signal generation means;

a means for detecting an overflow of said buffer memory and outputting an overflow detection signal;

a means for inactivating said write signal according to said overflow detection signal; and

a means for setting an address lower than a current address at said lower address generation means according to said overflow detection signal and for setting a write address composed of an upper address generated by said upper address generation means and a lower address generated by said lower address generation means as a writing start address for said communication cell data received next.

9. A communication data receiver as set forth in claim 8, wherein

said lower address generation means is reset to zero according to said overflow detection signal whereby the write address composed of the upper address generated by said upper address generation means and the lower address generated by said lower address generation means is set as the writing start address for said communication cell data received next.

10. A communication data receiver as set forth in claim 8, which further comprises:

a first counter constituting said lower address generation means;

said first counter incremented by said write signal;

a second counter constituting said upper address generation means; and

a means for checking a value read by said first counter and for resetting said first counter to zero and incrementing said second counter every time the read value coincides with the length of said received cell data.

11. A communication data receiver as set forth in claim 8, which further comprises:

a read signal generation means for generating a read signal for use in reading data from said buffer memory; and

a counter incremented by said write signal and decremented by said read signal;

wherein said overflow detection means outputting said overflow detection signal when the value read by said counter coincides with the maximum address of said buffer memory.

12. A communication data receiver as set forth in claim 11, wherein:

said third counter sets the value as the result of subtracting an address value generated by said lower address generation means from the read value coinciding with said maximum address value as a new count start value according to said overflow detection signal.

13. A communication data receiver as set forth in claim 8, wherein:

said write signal generation means comprises a flip flop set by the logical product of said synchronizing signal and said start detection signal to output the write signal for said buffer memory; and

said flip flop is reset by said overflow detection signal output from said overflow detection means to inactivate said write signal.

14. A communication data receiver for storing communication cell data received from a communication layer into a buffer memory and transferring said communication cell data to another communication layer, said communication data receiver comprising:

a means for detecting an overflow of said buffer memory;

a means for prohibiting said communication cell data from being written into said buffer memory according to said overflow detection; and

a means for setting a write address lower than a write address of said communication cell data being written in said buffer memory as a writing start address for said communication cell data received next according to said overflow detection.