Apparatus and method for testing a memory array

• US 5,663,965 A
• Filed: 10/06/1995
• Issued: 09/02/1997
• Est. Priority Date: 10/06/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Seymour, Edward Michael
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/539,932
• Time in Patent Office: 697 Days
• Field of Search: 371/22.3, 371/22.4, 371/21.5, 371/22.2, 371/37.6, 371/37.1, 365/201, 365/189
• US Class Current: 714/726
• CPC Class Codes: G11C 29/40 using compression techniques

Abstract

There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.

Claims

1. An apparatus for testing a memory array comprising:

a test data latch for receiving a test data vector on a serial input of said test data input latch and writing said test data vector in to a first location in said memory array;

an address buffer for receiving a test address vector on a serial input of said address buffer and applying said test address vector to said memory array;

an output latch for reading said test data vetor from said first location in said memory array; and

control logic for

     1) scanning said test data vector and said test address vector into said test data input latch and said address buffer, respectively,

     2) generating a write signal operable to cause said test data vector to be written from said test data input latch into said first lacation in said memory array and

     3) generating a read signal operable to cause said test data vector to be read from said first location in said memory array into said output latch.

2. The apparatus as set forth in claim 1, said control logic further comprising a shift register for receiving said test data vector from said output latch, using said test data vector as an input and performing a polynomial division on said input test data vector to generate a signature remainder indicating whether said first location contains a fault.

3. The apparatus as set forth in claim 1 wherein said control logic simultaneously scans said test data vector and said test address vector into said test data input latch and said address buffer, respectively.

4. The apparatus as set forth in claim 1 wherein said test address vector includes a first address in said memory array and a second address in said memory array adjacent to said first address and said control logic generates a write signal operable to cause a first test data vector to be written into said first address and generates a read signal operable to cause a second test data vector to be read from said second address immediately after said first data vector is written into said first address.

5. A processor comprising:

N memory arrays;

N test data input latches, each of said N test data input latches associated with a selected one of said N memory arrays, for receiving test data vectors on serial inputs of said N test data input latches and writing said test data vectors into a plurality of locations in said N memory arrays;

N address buffers, each of said N address buffers associated with a selected one of said N memory arrays, for receiving test address vectors on serial inputs of said N address buffers and applying said test address vector to said N memory arrays;

N output latches, each of said N output latches associated with a selected one of said N memory arrays, for reading said test data vectors from said plurality of locations in said N memory arrays; and

control logic comprising;

vector loading circuitry for scanning said test data vectors into said N test data input latches and scanning said test address vectors into said N address buffers;

data write circuitry for generating a plurality of write signals operable to cause said test data vectors to be written from said N test data input latches into said plurality of locations in said N memory arrays;

data read circuitry for generating a plurality of read signals operable to cause said test data vectors to be read from said plurality of locations in said N memory arrays into said N output latches.

6. The apparatus as set forth in claim 5, said control logic further comprising a multiple input shift register having at least N inputs for receiving said test data vectors from said N output latches, using said test data vectors as inputs and performing a polynomial division on said input test data vectors to generate a signature remainder indicating whether any of said plurality of locations in said N memory arrays contains a fault.

7. The apparatus as set forth in claim 6 wherein said control logic further comprises circuitry for 1) serially shifting said test data vectors from each of said N output latches into a selected one of said at least N inputs of said multiple input shift register, 2) causing said multiple input shift register to perform a polynomial division operation using said test data vectors, and 3) comparing a remainder calculated by said polynomial division operation with a signature remainder to determine if any of said plurality of locations in said N memory arrays contains a fault.

8. The apparatus as set forth in claim 5 wherein said vector loading circuitry simultaneously scans said test data vectors and said test address vectors into said N test data input latches and said N address buffers, respectively.

9. The apparatus as set forth in claim 5 wherein said test address vectors include a first address in each of said N memory arrays and a second address in each of said N memory array adjacent to said first address and said control logic generates a write signal operable to cause a first test data vector to be written into said first address and generates a read signal operable to cause a second test data vector to be read from said second address immediately after said first data vector is written into said first address.

10. A method of testing a memory array comprising the steps of:

serially shifting a test data vector into a test data input latch;

serially shifting a test address vector into an address buffer;

applying the test address vector in the address buffer to the address lines of the memory array;

writing the test data vector from the test data input latch into a first location in the memory array;

reading the test data vector from the first location in the memory array into an output latch;

serially shifting the test data vector from the output latch into a multiple input shift register; and

performing a polynomial division operation using the shifted test data vector as an input to generate thereby a signature remainder indicating whether the first location in the memory array contains a fault.

11. The method as set forth in claim 10 wherein the test data vector and the test address vector are simultaneously serially shifted into the test data input latch and the address buffer.