×

Apparatus and method for testing a memory array

  • US 5,663,965 A
  • Filed: 10/06/1995
  • Issued: 09/02/1997
  • Est. Priority Date: 10/06/1995
  • Status: Expired due to Fees
First Claim
Patent Images

1. An apparatus for testing a memory array comprising:

  • a test data latch for receiving a test data vector on a serial input of said test data input latch and writing said test data vector in to a first location in said memory array;

    an address buffer for receiving a test address vector on a serial input of said address buffer and applying said test address vector to said memory array;

    an output latch for reading said test data vetor from said first location in said memory array; and

    control logic for

         1) scanning said test data vector and said test address vector into said test data input latch and said address buffer, respectively,

         2) generating a write signal operable to cause said test data vector to be written from said test data input latch into said first lacation in said memory array and

         3) generating a read signal operable to cause said test data vector to be read from said first location in said memory array into said output latch.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×