Defect isolation using scan-path testing and electron beam probing in multi-level high density asics

• US 5,663,967 A
• Filed: 10/19/1995
• Issued: 09/02/1997
• Est. Priority Date: 10/19/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Gunda, Arun K., Prasad, Sharad, Lindberg, Grant A., De, Kaushik
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/545,462
• Time in Patent Office: 684 Days
• Field of Search: 371/26, 371/22.1, 371/22.3, 371/27
• US Class Current: 714/737
• CPC Class Codes: G01R 31/307 of integrated circuits
• CPC Class Codes: G01R 31/318544 Scanning methods, algorithms and patterns G01R31/3183 takes precedence
• CPC Class Codes: G06F 11/2257 using expert systems
• CPC Class Codes: G06F 11/2273 Test methods

Abstract

A method and apparatus for isolating faults in an integrated circuit reduces time and effort to precisely locate such faults. A fault dictionary is developed, which is a record of the errors a circuit'"'"'s modeled faults are expected to cause. The fault dictionary need only be generated once, and can be recalled for later testing of the same design. A failing circuit is subjected to test vectors and the erroneous outputs are logged, and then all failing scan test vectors are mapped into simulation scan patterns. Faults in the circuit are localized to a more narrowly defined area in which faults in the circuit may occur. If the area, even after localization, is too large, additional test patterns are developed and the device is subjected to another round of tests. The redefinition of test patterns is repeated until possible fault locations are sufficiently localized. The device is then probed to precisely locate the fault(s).

Claims

1. A method of isolating a defect in an integrated circuit device, comprising the steps of:

defining a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device using scan test vectors which are included in said fault dictionary said faults included predefined faults and failures from the design simulation of the integrated circuit device;

testing the integrated circuit device with said scan test vectors;

collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device;

mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns;

performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, probing the scan chain to isolate the fault;

if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator;

creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device, based on said simulation scan patterns, to localize possible fault candidates in the integrated circuit device;

if the list of suspect faults is sufficiently small, probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic;

if the list of suspect faults is not sufficiently small, creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and

retesting the integrated circuit device with said additional scan test vectors.

2. The method of claim 1 wherein the step of probing the integrated circuit device is done with an electron beam prober.

3. An integrated circuit device defect isolation testing apparatus, comprising:

means for storing a fault dictionary of faults anticipated from specific scan patterns applied to a design simulation of an integrated circuit device, including predefined faults and failures from the design simulation of the integrated circuit device using said scan test vectors;

means for testing the integrated circuit device with said scan test vectors from said fault dictionary;

means for collecting outputs from the integrated circuit device, the outputs generated by said scan test vectors testing the integrated circuit device;

means for mapping said scan test vectors, which cause incorrect outputs from the integrated circuit device, with corresponding ones of said outputs from the integrated circuit device into simulation scan patterns;

means for performing, in response to said simulation scan patterns, a scan integrity test of sequential circuitry defining a scan chain in the integrated circuit device and, if the scan integrity test fails, means for probing the scan chain to isolate the fault;

if the scan integrity test passes, providing said simulation scan patterns to a diagnostic software program simulator;

means for creating, by said diagnostic software program simulator, a list of suspect faults in combinational logic of the integrated circuit device based on said simulation scan patterns to localize possible fault candidates in the integrated circuit device;

if the list of suspect faults is sufficiently small, means for probing a selected area of the combinational logic of the integrated circuit device to determine the location of the fault in the combinational logic;

if the list of suspect faults is not sufficiently small, means for creating additional scan test vectors so as to further localize possible fault candidates in the integrated circuit device; and

means for retesting the integrated circuit device with said additional scan test vectors.

4. The apparatus of claim 3, wherein the means for probing is an electron beam prober.