Data processor for performing a comparison instruction using selective enablement and wired boolean logic

• US 5,664,134 A
• Filed: 02/23/1995
• Issued: 09/02/1997
• Est. Priority Date: 03/31/1993
• Status: Expired due to Fees

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Seaton, Robert W. Jr., Gallup, Michael G., Goke, L. Rodney
• Primary Examiner(s): Donaghue, Larry D.
• Application Number:
  US08/393,602
• Time in Patent Office: 922 Days
• Field of Search: 395/375, 395/800, 395/21, 395/24, 395/2.48
• US Class Current: 712/245
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/78 comprising a single central processing unit
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 7/49921 Saturation, i.e. clipping the result to a minimum or maximum value
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: G06F 7/57 Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations G06F7/49, G06F7/491 take precedence
• CPC Class Codes: G06F 8/445 Exploiting fine grain parallelism, i.e. parallelism at instruction level run-time instruction scheduling G06F9/3836
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 9/30 Arrangements for executing machine instructions, e.g. instruction decode for executing microinstructions G06F9/22
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/30065 Loop control instructions; iterative instructions, e.g. LOOP, REPEAT
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30079 Pipeline control instructions, e.g. multicycle NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/3802 : Instruction prefetching
• CPC Class Codes: G06F 9/3812 : with instruction modification, e.g. store into instruction stream
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3867 : using instruction pipelines
• CPC Class Codes: G06F 9/3877 : using a slave processor, e.g. coprocessor peripheral processor G06F13/12; vector processor G06F15/8053
• CPC Class Codes: G06F 9/3887 : controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/38873 : Iterative single instructions for multiple data lanes [SIMD]
• CPC Class Codes: G06F 9/3889 : controlled by multiple instructions, e.g. MIMD, decoupled access or execute
• CPC Class Codes: G06N 3/063 : using electronic means

Abstract

A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.

Claims

1. A data processor, comprising:

storage means for storing a comparison instruction which specifies a number of bits to be compared;

an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction;

instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals;

a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction; and

a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state.

2. The data processor of claim 1 wherein the data value stored in each of the plurality of enabled processing elements has a predetermined bit width of n, where n is a positive integer.

3. The data processor of claim 2 wherein the first portion of the data value is a most significant bit of the data value.

5. The data processor of claim 2 further comprising:

a modification circuit for selectively modifying a portion of the plurality of enable values in response to one of the first and second logic states of the comparison conductor.

6. The data processor of claim 5 wherein one of the plurality of enabled processing elements is enabled to provide the data value stored therein to the comparison conductor when a corresponding one of the plurality of enable values is asserted.

7. The data processor of claim 5 wherein one of the plurality of enabled processing elements is distilled from participating in execution of the comparison instruction when a corresponding one of the plurality of enable values is negated.

8. The data processor of claim 5 wherein the plurality of enable values selectively enable the plurality of enabled processing elements to provide the first digital data value to the comparison conductor.

9. The data processor of claim 8 wherein the modification circuit:

leaves one of the plurality of enable values unmodified when the comparison conductor is in the first logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the first logic state, and

leaves the one of the plurality of enable values unmodified when the comparison conductor is in the second logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.

10. The data processor of claim 8 wherein the modification circuit modifies one of the plurality of enable values when the comparison conductor is in the first logic state and the first portion of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.

11. The data processor of claim 1 wherein the comparison instruction determines a first portion of the plurality of processing elements which have a maximum value in the first portion of the data value.

12. The data processor of claim 1 wherein each of the plurality of enabled processing elements further comprises:

a logic circuit for complementing the first portion of the data value to provide a first complemented data value to the comparison conductor.

13. The data processor of claim 12 wherein the comparison instruction determines a first portion of the plurality of enabled processing elements which have a minimum value in the first portion of the data value.

14. The data processor of claim 12 wherein the first portion of the data value is a sign bit.

15. The data processor of claim 1 further comprising a control storage circuit for storing a control value, the control value indicating the comparison instruction uses one of a signed operand and an unsigned operand, the control storage circuit being coupled to the instruction execution means.

16. The data processor of claim 1 further comprising:

a switch circuit which is coupled to the comparison conductor; and

a first integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the first integrated circuit pin to the comparison conductor.

17. The data processor of claim 16 wherein the switch circuit selectively couples the first integrated circuit pin to the comparison conductor in response to the comparison instruction.

18. The data processor of claim 17 wherein the first integrated circuit pin is coupled to a first external integrated circuit pin of an external data processor, the first integrated circuit pin coupling the comparison conductor to the first external integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor.

19. The data processor of claim 18 wherein the first integrated circuit pin transfers control infomarion when the data processor is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the data processor is in a second mode of operation.

20. The data processor of claim 16 further comprising a second integrated circuit pin, the second integrated circuit pin being coupled to the switch circuit.

4. The data processor of clam 1 further comprising:

a first storage circuit for storing a pIurality of enable values, each of the plurality of enable values corresponding to one of the plurality of enabled processing elements.

21. A method of comparing a plurality of data values in a data processor, comprising the steps of:

receiving a comparison instruction which specifies a number of bits to be compared;

decoding the comparison instruction to provide a plurality of control signals;

determining which of a plurality of processing elements are enabled, each processing element of an enabled portion of the plurality of processing elements providing a first portion of a data value stored therein to a comparison line;

providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state;

providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state; and

selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements.

22. The method of claim 21 wherein each of the plurality of enable values selectively enable a corresponding one of the enabled portion of the plurality of processing elements to provide the digital data value stored therein.

23. The method of claim 21 further comprising the step of:

negating the one of the plurality of enable bits when the first portion of the data value provided by the corresponding one of the enabled portion of the plurality of processing elements is in a different logic state than the comparison line.

24. The method of claim 23 further comprising the step of:

insuring that one of the plurality of enable bits remains in an asserted state when the first portion of the data value provided by a corresponding one of the enabled portion of the plurality of processing elements in a same logic state as the comparison line.

25. The method of claim 23 further comprising the steps of:

accessing a second portion of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted;

providing the second portion of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line;

providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the second portion of the data value stored therein in the first logic state;

providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the second portion of the data value stored therein in the second logic state; and

negating one of the plurality of enable bits when the second portion of the data value is in a different logic state than the comparison line.

26. The method of claim 21 wherein each of the plurality of data values stored in each one of the plurality of processing elements has a plurality of n bits, where n is a positive integer value.

27. The method of claim 26 wherein the first portion of each of the plurality of data values is a most significant bit of the data value.

28. The method of claim 27 further comprising the steps of:

i) accessing a next one of the plurality of bits of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted;

ii) providing the next one of the plurality of bits of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line;

iii) providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the first logic state;

iv) providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the second logic state;

v) negating one of the plurality of enable values when the next one of the plurality of bits of the data value is in a different logic state than the comparison line; and

vi) repeating steps i) through v) for a predetermined number of repetitions as specified by the number of bits to be compared in the comparison instruction.

29. The method of claim 28 wherein the predetermined number of repetitions is equal to a value of (n-1).

30. The method of claim 28 wherein the predetermined number of repetitions is less than the value of (n-1).

31. The method of claim 28 wherein the comparison instruction determines a first portion of the plurality of processing elements which store an unsigned data value having a maximum value.

32. The method of claim 28 further comprising the step of:

inverting the most significant bit of the data value provided by each of the plurality of processing elements before providing the most significant bit of the data value to the comparison line.

33. The method of claim 32 wherein the comparison instruction determines a second portion of processing elements in the plurality of processing elements which store a two'"'"'s complement signed data value having a maximum value.

34. The method of claim 28 further comprising the step of:

inverting each of the plurality of bits of the data value provided by each of the plurality of processing elements before providing each of the plurality of bits to the comparison line.

35. The method of claim 34 wherein the comparison instruction determines a third portion of processing elements in the plurality of processing elements which store an unsigned data value having a minimum value.

36. The method of claim 28 further comprising the step of:

inverting a portion of the plurality of bits of the data value provided by each of the plurality of processing elements before providing the portion of the plurality of bits to the comparison line, the portion of the plurality of bits not including the most significant bit of the data value.

37. The method of claim 36 wherein the comparison instruction determines a fourth portion of processing elements in the plurality of processing elements which store a two'"'"'s complement signed data value having a minimum value.

38. A data processing system, comprising:

a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising;

storage means for storing a comparison instruction which specifies a number of bits to be compared;

an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction;

instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals;

a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction;

a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state; and

each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors.

39. The data processor of claim 38 wherein the first portion of the data value is equal to the number of bits to be compared specified by the comparison instruction.

40. The data processing system of claim 38 wherein the array comprises at least one row and at least one column.

41. The data processing system of claim 40 wherein the first one of the plurality of data processors is in a same row of the array as the second one of the plurality of data processors.

42. The data processing system of claim 40 wherein the first one of the plurality of data processors is in a same column of the array as the second one of the plurality of data processors.

43. The data processing system of claim 38 further comprising:

a first storage circuit for storing a plurality of enable values, each of the plurality of enable values corresponding to one of the plurality of enabled processing elements.

44. The data processing system of claim 43 further comprising:

a modification circuit for selectively modifying each one of the plurality of enable values in response to one of the first and second logic states of the comparison conductor.

45. The data processing system of claim 44 wherein each one of the plurality of enabled processing elements participates in execution of the comparison instruction when a corresponding one of the plurality of enable values is asserted.

46. The data processing system of claim 44 wherein one of the plurality of enabled processing elements is disabled from participating in execution of the comparison instruction when a corresponding one of the plurality of enable values is negated.

47. The data processing system of claim 44 wherein the modification circuit negates one of the plurality of enable values when the comparison conductor is in the first logic state and the first bit of the data value provided by one of the plurality of enabled processing elements corresponding to the one of the plurality of enable values is in the second logic state.

48. The data processing system of claim 44 wherein the comparison instruction determines a first portion of the plurality of enabled processing elements in each of an enabled portion of the plurality of data processors which have a maximum value in the first bit of the data value.

49. The data processing system of claim 44 wherein each one of the plurality of enabled processing elements further comprises:

a logic circuit for selectively compIementing at least a portion of the data value to provide a first complemented data value to the comparison conductor.

50. The data processing system of claim 49 wherein the portion of the data value is a most significant bit of the data value.

51. The data processing system of claim 38 wherein each of the data processors further comprises:

a switch circuit which is coupled to the comparison conductor; and

an integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the integrated circuit pin to the comparison conductor.

52. The data processing system of claim 51 wherein the switch circuit selectively couples the integrated circuit pin to the comparison conductor in response to a global comparison instruction.

53. The data processing system of claim 52 wherein a first integrated circuit pin of a first one of the plurality of data processors is coupled to a second integrated circuit pin of a second one of the plurality of data processors, the first integrated circuit pin coupling the comparison conductor to the second integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor.

54. The data processing system of claim 53 wherein the first integrated circuit pin transfers control information when the first one of the plurality of data processors is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the first one of the plurality of data processors is in a second mode of operation.

55. A data processor, comprising:

storage means for storing a comparison instruction;

an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction;

instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals;

a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the enabled plurality of processing elements being coupled to the instruction execution means, the instruction execution means selecting each of the plurality of enabled processing elements to output a first portion of the data value stored therein during execution of the comparison instruction;

a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first portion of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first portion of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first portion of the data value provided by each of the plurality of enabled processing elements is in the second logic state;

a switch circuit which is coupled to the comparison conductor; and

a first integrated circuit pin which is coupled to the switch circuit, the switch circuit selectively coupling the first integrated circuit pin to the comparison conductor in response to the comparison instruction,

wherein the first integrated circuit pin is coupled to a first external integrated circuit pin of an external data processor, the first integrated circuit pin coupling the comparison conductor to the first external integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor; and

wherein the first integrated circuit pin transfers control information when the data processor is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the data processor is in a second mode of operation.

56. A method of comparing a plurality of data values in a data processor, comprising the steps of:

i) receiving a comparison instruction;

ii) decoding the comparison instruction to provide a plurality of control signals;

iii) determining which of a plurality of processing elements are enabled, wherein each of the plurality of data values stored in each one of the plurality of processing elements has a plurality of n bits, where n is a positive integer value and wherein each processing element of an enabled portion of the plurality of processing elements provides a first portion of a data value stored therein to a comparison line, the first portion of each of the plurality of data values being a most significant bit of the data value;

iv) providing the comparison line in a first logic state when at least one of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the first logic state;

v) providing the comparison line in a second logic state when each of the enabled portion of the plurality of processing elements provides the first portion of the data value stored therein in the second logic state;

vi) selectively modifying a plurality of enable bits in response to a logic state of the comparison line, each of the plurality of enable bits corresponding to one of the enabled portion of the plurality of processing elements;

vii) accessing a next one of the plurality of bits of the data value stored in each one of the enabled portion of the plurality of processing elements, each one of the enabled portion of the plurality of processing elements having a corresponding one of the plurality of enable values which is asserted;

viii) providing the next one of the plurality of bits of the data value output by each one of the enabled portion of the plurality of processing elements to a comparison line;

ix) providing the comparison line in the first logic state when at least one of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the first logic state;

providing the comparison line in the second logic state when each of the enabled portion of the plurality of processing elements provides the next one of the plurality of bits of the data value stored therein in the second logic state;

xi) negating one of the plurality of enable values when the next one of the plurality of bits of the data value is in a different logic state than the comparison line;

xii) repeating steps vii) through xi) for a predetermined number of repetitions; and

xiii) inverting a portion of the plurality of bits of the data value provided by each of the plurality of processing elements before providing the portion of the plurality of bits to the comparison line, the portion of the plurality of bits not including the most significant bit of the data value.

57. A data processing system, comprising:

a plurality of data processors arranged in an array, each one of the plurality of data processors, comprising;

storage means for storing a comparison instruction;

an instruction decode circuit for decoding the comparison instruction to provide a plurality of control signals, the instruction decode circuit coupled to the storage means for receiving the comparison instruction;

instruction execution means for controlling execution of the comparison instruction in response to the plurality of control signals, the instruction execution means coupled to the instruction decode circuit for receiving the plurality of control signals;

a plurality of enabled processing elements wherein each one of the plurality of enabled processing elements stores a data value, each one of the plurality of enabled processing elements being coupled to the instruction execution means, the instruction execution means selecting the plurality of enabled processing elements to output a first bit of the data value stored therein during execution of the comparison instruction;

a comparison conductor connected to each one of the plurality of enabled processing elements for receiving the first bit of the data value stored therein, the comparison conductor performing a comparison operation in response to execution of the comparison instruction, the comparison conductor being in a first logic state when the first bit of the data value provided by at least one of the plurality of enabled processing elements is in the first logic state, the comparison conductor being in a second logic state when the first bit of the data value provided by each of the plurality of enabled processing elements is in the second logic state;

each one of the plurality of data processors being selectively coupled to an adjacent data processor to communicate information, the comparison conductor of a first one of the plurality of data processors being coupled to the comparison conductor of a second one of the plurality of data processors;

a switch circuit which is coupled to the comparison conductor;

a first integrated circuit pin; and

a second integrated circuit pin, wherein the first integrated circuit pin of a first one of the plurality of data processors is coupled to a second integrated circuit pin of the second one of the plurality of data processors, the first integrated circuit pin coupling the comparison conductor to the second integrated circuit pin when the switch circuit selectively couples the first integrated circuit pin to the comparison conductor, and wherein the first integrated circuit pin transfers control information when the first one of the plurality of data processors is in a first mode of operation and the first integrated circuit pin is selectively coupled to the comparison conductor when the first one of the plurality of data processors is in a second mode of operation.