High speed access to PC card memory using interrupts

• US 5,664,198 A
• Filed: 10/26/1994
• Issued: 09/02/1997
• Est. Priority Date: 10/26/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Pierce, Michael E., Chen, Chengwu, Foote, James L. III
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/329,230
• Time in Patent Office: 1,042 Days
• Field of Search: 395/733, 395/735, 395/775, 395/280, 395/375, 395/311, 395/846, 395/651, 395/652, 395/309, 395/427, 395/828
• US Class Current: 710/260
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A system for accessing attribute memory on a card using the interrupt capability of a microcontroller on the PCMCIA card intended to perform I/O functions for the host. The attribute memory interfaces directly with the microcontroller. A PLD is connected between the host bus and the microcontroller decodes the host'"'"'s bus signals and generates an interrupt signal when it detects a request for access to the attribute memory which signal is supplied to the microcontroller. Upon receipt of the interrupt signal, the microcontroller runs a special routine that accesses attribute memory and supplies the results to the host. The PCMCIA card has a configured state in which the host has read the configuration information from attribute memory and has allocated necessary system resources. The PCMCIA card is in an unconfigured state if the foregoing has not been accomplished. The programmable logic device contains an AND gate having one of its inputs connected to the lines of the bus relating to the I/O function and a second input connected to the microprocessor for receiving a card enable signal, having at least two logic states. The control signals are passed to the microcontroller when the card enable signal is in one of the two logic states. The method consists of the steps of decoding the bus signals; when the host requests access to attribute memory, generate an interrupt signal and supply it to the microcontroller; the microcontroller runs an interrupt routine that includes saving the microcontroller registers, disabling the I/O functions, accessing the attribute memory, and providing the results to the host.

Claims

1. In a method of accessing memory located on a Personal Computer Memory Card International Association (PCMCIA) card within a host computer, said PCMCIA card comprising a PCMCIA bus, attribute memory, common memory and I/O space and operating under the control of a microcontroller on said PCMCIA card to perform at least one I/O function, wherein said microcontroller contains registers, and wherein said PCMCIA card has a configured and unconfigured state, and wherein said host includes a bus having address, data and control lines connected through an interface to said PCMCIA card bus, and wherein logic circuitry is provided on said PCMCIA card for monitoring said PCMCIA card bus, decoding said PCMCIA card bus signals and generating non-maskable interrupts as a result thereof, which interrupts are supplied to said microcontroller, said method comprising the following steps:

decoding said PCMCIA card bus signals to determine when said host has made a request for access to attribute memory;

generating a non-maskable interrupt when said attribute memory access is detected;

running an interrupt routine located in said memory wherein said interrupt routine comprises the following steps;

disconnecting said I/O function of said PCMCIA card from said host;

saving said registers of said microcontroller;

performing said access to attribute memory requested by said host;

providing the results of said attribute memory access to said host;

testing to determine if said PCMCIA card has been configured;

if said test indicates that said PCMCIA card is configured, reconnect said I/O function of said PCMCIA card to said host; and

return control of said microcontroller to the location in code from which it was taken upon the occurrence of said interrupt.

2. The method of claim 1 wherein said PCMCIA card contains configuration information structure (CIS) information in said attribute memory.

3. The method of claim 2 wherein said bus signals to be decoded are said control signals.

4. A computer system comprising:

a host computer having a host bus with address, data and control lines;

a personal computer (PC) card having a PC card bus and microcontroller with associated memory, said memory being divided into at least a first section storing a startup routine and configuration information for said PC card and a second section storing I/O information used to perform at least one I/O function for said host, and wherein said startup routine and configuration are not available to said host through software commands alone after said startup routine has been completed;

an interface for connecting said host bus to said PC card bus;

logic on said PC card connected to and monitoring signals on said PC card bus and supplying an interrupt signal to said microcontroller upon decoding memory access commands from said host that request information stored in said first section of memory; and

means in said microcontroller responsive to said interrupt signal for supplying said startup routine and configuration information stored in said first section of memory to said host computer.

5. The system of claim 4 wherein said means in said microcontroller responsive to said interrupt signal for supplying said information stored in said first section of memory to said host computer comprises an interrupt routine running instructions stored in said memory.

6. The system of claim 5 wherein said interface operates under a signal protocol and wherein said signal protocol management for said PC card is performed by said microcontroller.

7. The system of claim 6 further characterized by logic circuitry connected between said PC card bus and said microcontroller for disconnecting said I/O functions of said PC card from said host if said host has not read said configuration information from said first section of memory and has not completed said startup routine by allocating system resources necessary to perform said I/O function.

8. The system of claim 7 wherein said logic circuitry connected between said PC card bus and said microcontroller comprises:

circuitry having as a first input connected to said control lines of said PC card bus relating to I/O space, an output connected to said microcontroller, and a second input connected to said microprocessor for receiving a signal having at least two logic states, said circuitry adapted to cause signals on said control lines of said PC card bus to be passed through to said microcontroller when said second input signal is in a first state and not passed to said microcontroller when said second input signal is in other than said first state.