Microcomputer free from control of central processing unit (CPU) for receiving and writing instructions into memory independent of and during execution of CPU

• US 5,664,199 A
• Filed: 03/16/1995
• Issued: 09/02/1997
• Est. Priority Date: 05/12/1992
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Kuwahara, Kazuyoshi
• Primary Examiner(s): Lim, Krisna
• Application Number:
  US08/405,918
• Time in Patent Office: 901 Days
• Field of Search: 395/375, 395/775
• US Class Current: 710/261
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 11/3648 using additional hardware
• CPC Class Codes: G06F 11/3652 in-circuit-emulation [ICE] arrangements

Abstract

A microcomputer includes a program memory storing a string of instructions for a program, a central processing unit executing each instruction read out from the program memory, an instruction memory having an address area different from the program memory, a serial communication unit responding to data supplied in series thereto and writing instructions into the instruction memory in synchronism with an operation of the central processing unit, and an interrupt control unit responding to an interrupt request to cause the central processing unit to suspend the execution of the program stored in the program memory and to then execute instructions read out from the instruction memory to output internal conditions.

Claims

1. A microcomputer comprising:

a program memory for storing first instructions for a program;

a central processing unit for executing said first instructions stored in said program memory;

an instruction memory provided independently of said program memory;

a communication unit for receiving a plurality of second instructions from an external source and for writing said second instructions into said instruction memory independently of and during execution of said first instructions by said central processing unit; and

means for causing said central processing unit to suspend the execution of said first instructions and to then execute said second instructions written into said instruction memory,

said central processing unit transferring data indicative of internal conditions thereof to said communication unit by executing said second instructions and thereafter resuming the execution of said first instructions,

said communication unit transferring said data to said external source independently of execution of any one of said first and second instructions,

wherein said communication unit includes a data register, said central processing unit accessing said data register by executing said second instructions to transfer and store said data to said data register, and

wherein said communication unit further includes a transfer unit responding to a command from said external source to transfer said data stored in said data register to said external source independently of the execution of said first and second instructions by said central processing unit.

2. A microcomputer comprising:

a program memory for storing first instructions for a program;

a central processing unit for executing said first instructions;

an instruction memory provided independently of said program memory;

an instruction register provided independently of said program memory and said instruction memory;

a communication unit including first means free from control of said central processing unit and responsive to a first command from an external source for receiving a plurality of second instructions from said external source in a serial data transfer manner and writing each of said second instructions into said instruction register, said communication unit further including second means free from control of said central processing unit and responsive to a second command from said external source for producing instruction write-enable information;

a memory control unit free from control of said central processing unit and responding to said instruction write-enable information to write each of said second instructions stored in said instruction register into said instruction memory;

a data register operatively coupled to said central processing unit; and

control means for causing said central processing unit to suspend execution of said first instructions and to then execute said second instructions stored in said instruction memory,

said central processing unit accessing said data register by executing said second instructions to store in said data register data indicative of internal conditions thereof and thereafter resuming the execution of said first instructions,

said communication unit further including third means free from control of said central processing unit and responsive to a third command from said external source for transmitting said data stored in said data register to said external source in said serial data transfer manner.

3. The microcomputer as claimed in claim 2, wherein said communication unit further includes fourth means free from control of said central processing unit and responsive to a fourth command from said external source for receiving and outputting a break address,

wherein said control means includes an address register,

said fourth means writing said break address into said address register, said control means further including an address comparator for comparing said break address stored in said address register with an instruction address designating one of said first instructions to be executed and for producing an interrupt signal when said break address is coincident with said instruction address and an interrupt control unit responding to said interrupt signal to cause said central processing unit to suspend the execution of said first instructions and to then execute said second instruction.

4. The microcomputer as claimed in claim 2, wherein said control means includes an interrupt control unit responding to an interrupt request signal issued by said external source and causing said central processing unit to suspend the execution of said first instructions and to then execute said second instructions.

5. The microcomputer as claimed in claim 2, further comprising a reset control circuit responding to a first control signal to bring said central processing unit into a reset state to stop an operation of said central processing unit,

said communication unit further including means responsive to a reset command from said external source for generating said first control signal,

said second instructions being written into said instruction register by said second means and then into said instruction memory by said memory control unit during said reset state of said central processing unit.

6. The microcomputer as claimed in claim 2, wherein said communication unit further includes fourth means free from control of said central processing unit and responsive to a fourth command from said external source for receiving and outputting a break address, and

wherein said control means includes an address register.

7. The microcomputer as claimed in claim 6, wherein said fourth means writes said break address into said address register,

said control means further including an address comparator for comparing said break address stored in said address register with an instruction address designating one of said first instructions to be executed and for producing an interrupt signal when said break address is coincident with said instruction address and an interrupt control unit responding to said interrupt signal to cause said central processing unit to suspend the execution of said first instructions and to then execute said second instruction.

8. The microcomputer as claimed in claim 2, further comprising a reset control circuit responding to a first control signal to bring said central processing unit into a reset state to stop an operation of said central processing unit.

9. The microcomputer as claimed in claim 8, wherein said communication unit further includes means responsive to a reset command from said external source for generating said first control signal,

said second instructions being written into said instruction register by said second means and then into said instruction memory by said memory control unit during said reset state of said central processing unit.

10. A microcomputer comprising:

a program memory for storing a first instruction for a program;

a processor for executing said first instruction stored in said program memory;

an instruction memory provided independently of said program memory;

a communication unit for independently receiving a second instruction from an external source and for writing said second instruction into said instruction memory independently of and during execution of said first instruction by said processor; and

means for causing said processor to suspend the execution of said first instruction and to then execute said second instruction written into said instruction memory,

wherein said communication unit includes a data register, said processor accessing said data register by executing said second instruction to transfer and store data to said data register, and

wherein said communication unit further includes a transfer unit responding to a command from said external source to transfer said data stored in said data register to said external source independently of the execution of said first and second instructions by said processor.

11. The microcomputer as claimed in claim 10, wherein said data is indicative of internal conditions of said processor, and

wherein said processor transfers said data to said communication unit by executing said second instruction and thereafter resumes the execution of said first instruction.

12. The microcomputer as claimed in claim 10, wherein said communication unit transfers said data to said external source independently of execution of any one of said first instruction and said second instruction.

13. The microcomputer as claimed in claim 11, wherein said communication unit transfers said data to said external source independently of execution of any one of said first instruction and said second instruction.