Method of fabricating a self-aligned contact trench DMOS transistor structure

• US 5,665,619 A
• Filed: 05/13/1996
• Issued: 09/09/1997
• Est. Priority Date: 05/01/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Bencuya, Izak, Kwan, Sze-Hon
• Primary Examiner(s): Nguyen, Tuan H.
• Application Number:
  US08/645,446
• Time in Patent Office: 484 Days
• Field of Search: 437/40, 437/41, 437/67, 437/203, 148/DIG. 126
• US Class Current: 438/270
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench DMOS transistor structure includes a contact to the transistor'"'"'s source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.

Claims

1. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising the sequential steps of:

forming a layer of silicon oxide on an underlying layer of N-type epitaxial silicon;

forming a layer of nitride over the silicon oxide layer;

forming a deposited oxide layer over the nitride layer to define an oxide/nitride/oxide (ONO) sandwich;

defining a trench mask over the deposited oxide layer to expose pre-selected surface regions of the deposited oxide layer;

etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed deposited oxide surface regions;

etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer;

removing the deposited oxide layer;

forming silicon oxide on exposed surfaces of the trenches;

depositing a layer of polysilicon to fill the trenches;

etching the polysilicon layer to define polysilicon gate regions in the trenches, said polysilicon gate regions being planarized to an upper surface of the nitride layer;

growing a polyoxide pad on the exposed upper surface of each polysilicon gate region;

implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches;

defining an N+ source mask to use as a mask to introduce N-dopant to define N+ source regions adjacent to the trenches;

oxidizing the polyoxide pads to form oxide spacers that extend over the source regions;

implanting P-dopant into the active device regions to form a P+ body ohmic contact region between the source regions in the active region; and

forming a conductive layer over the polyoxide pads and the oxide spacers for contact with the ohmic contact region.

2. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising the sequential steps of:

forming a layer of silicon oxide on an underlying layer of N-type epitaxial silicon;

forming a layer of nitride over the silicon oxide layer;

forming a deposited oxide layer over the nitride layer to define an oxide\nitride\oxide (ONO) sandwich;

defining a trench mask over the deposited oxide layer to expose pre-selected surface regions of the deposited oxide layer;

etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed deposited oxide surface regions;

etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer;

removing the deposited oxide layer;

forming silicon oxide on exposed surfaces of the trenches;

depositing a layer of polysilicon to fill the trenches;

etching the polysilicon layer to define polysilicon gate regions in the trenches, said polysilicon gate regions being etched to an upper surface of the silicon oxide;

forming a second deposited oxide layer;

etching the second deposited oxide layer to define oxide pads on the upper surface of each polysilicon gate region;

implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches;

defining an N+ source mask to use as a mask to introduce N-dopant to define N+ source regions adjacent to the trenches;

forming a third deposited oxide layer;

etching the third deposited oxide layer to define oxide spacers on the sidewalls of the oxide pads such that the oxide spacers extend over the source regions;

implanting P-dopant into the active device regions to form a P+ body ohmic content region between the source regions in the active region; and

forming a conductive layer over the oxide pads and the oxide spacers for contact with the ohmic contact region.

3. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising the sequential steps of:

forming a layer of silicon oxide on an underlying layer of N-type epitaxial silicon;

forming a layer of nitride over the silicon oxide layer;

forming a first deposited oxide layer over the nitride layer to define an oxide\nitride\oxide (ONO) sandwich;

defining a trench mask over the first deposited oxide layer to expose pre-selected surface regions of the first deposited oxide layer;

etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed first deposited oxide surface regions;

etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer;

removing the first deposited oxide layer;

forming silicon oxide on exposed surfaces of the trenches;

depositing a layer of polysilicon to fill the trenches;

etching the polysilicon layer to define polysilicon gate regions in the trenches, said polysilicon gate regions being etched to an upper surface of the silicon oxide;

forming a second deposited oxide layer;

etching the second deposited oxide layer to define oxide pads on the upper surface of each polysilicon gate region;

implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches;

defining an N+ source mask to use as a mask to introduce N-dopant to define N+ source regions adjacent to the trenches;

implanting P-dopant into the active device regions to form a P+ body ohmic content region between the source regions in the active region; and

forming a conductive layer over the oxide pads and the oxide spacers for contract with the ohmic contact region.