Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal

• US 5,665,639 A
• Filed: 02/23/1994
• Issued: 09/09/1997
• Est. Priority Date: 02/23/1994
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Maier, Lothar, Seppala, Bryan R., Backer, Todd G.
• Primary Examiner(s): GRAYBILL, DAVID E
• Application Number:
  US08/200,673
• Time in Patent Office: 1,294 Days
• Field of Search: 437/183, 437/194, 437/174, 437/247, 228/180.22, 148/3, 148/4
• US Class Current: 438/15
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03912 the bump being used as a mask for patterning the bonding area
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A rapid thermal anneal (RTA) process minimizes the intermixing of materials between a bump and a bonding pad so as to provide for a more reliable and durable interconnect between the bump and the bonding pad and so as to allow the probing of wafers prior to bumping. A barrier layer is formed over the bonding pads of devices formed over a semiconductor substrate. Bumps are then formed over the bonding pads and are annealed for a short time at a high temperature so as to soften the bumps for later assembly in a semiconductor package. As a result of this quick annealing process, the intermixing of materials between the bumps and the bonding pads is minimized. This is so despite any decreased step coverage of the barrier layer over probe marks on the bonding pads which resulted from testing the wafer. Accordingly, wafers may now be tested prior to bumping, thus saving the cost, time, and process steps typically incurred in bumping wafers having a zero or low yield of properly functioning semiconductor devices.

Claims

1. A method for use in semiconductor device fabrication comprising the steps of:

(a) forming over a semiconductor substrate a semiconductor device having a bonding pad;

(b) forming over the semiconductor device a layer having an opening which exposes a portion of the bonding pad;

(c) forming a bump comprising gold over the exposed portion of the bonding pad; and

(d) annealing the bump with a rapid thermal anneal.

2. The method of claim 1, further comprising the step of:

(e) forming an interconnection between the bump and a semiconductor package.

3. The method of claim 1, further comprising the step of probing the bonding pad to test the semiconductor device prior to the bump forming step (c).

4. The method of claim 1, further comprising the step of forming a barrier layer over the exposed portion of the bonding pad prior to the bump forming step (c).

5. The method of claim 4, wherein the barrier layer forming step comprises the steps of forming a first adhesion sublayer over at least the exposed portion of the bonding pad, forming a barrier sublayer over the first adhesion sublayer, and forming a second adhesion sublayer over the barrier sublayer.

6. The method of claim 1, wherein the bonding pad comprises aluminum.

7. The method of claim 1, wherein the annealing step (d) comprises the step of heating the bump at a temperature between approximately 250 degrees Celsius and approximately 500 degrees Celsius for a period of time between approximately 15 seconds and approximately 60 seconds.

8. The method of claim 7, wherein the temperature is between approximately 350 degrees Celsius and approximately 500 degrees Celsius.

9. The method of claim 8, wherein the temperature is between approximately 425 degrees Celsius and approximately 475 degrees Celsius and wherein the period of time is between approximately 20 seconds and approximately 40 seconds.

10. The method of claim 9, wherein the temperature is approximately 450 degrees Celsius and wherein the period of time is approximately 30 seconds.

18. The method of claim 2, wherein the forming step (e) includes the step of using a tape automated bonding process.

19. The method of claim 5, wherein the first adhesion sublayer comprises titanium tungsten (TiW), the barrier sublayer comprises titanium tungsten nitride (TiWN), and the second adhesion sublayer comprises titanium tungsten (TiW).

11. A method for use in semiconductor device fabrication comprising the steps of:

(a) forming over a semiconductor substrate a semiconductor device having a bonding pad;

(b) forming over the semiconductor device a layer having an opening which exposes a portion of the bonding pad;

(c) probing the bonding pad to test the semiconductor device;

(d) forming, after the probing step (c), a bump comprising gold over the exposed portion of the probed bonding pad;

(e) annealing the bump with a rapid thermal anneal; and

(f) forming an interconnection between the bump and a semiconductor package.

12. The method of claim 11, wherein the forming step (f) includes the step of using a tape automated bonding process.

13. The method of claim 11, wherein the method further comprises a barrier layer forming step, wherein said barrier layer forming step comprises the steps of forming a first adhesion sublayer over the exposed portion of the bonding pad, forming a barrier sublayer over the first adhesion sublayer, and forming a second adhesion sublayer over the barrier sublayer.

14. The method of claim 11, wherein the annealing step (e) comprises the step of heating the bump at a temperature between approximately 250 degrees Celsius and approximately 500 degrees Celsius for a period of time between approximately 15 seconds and approximately 60 seconds.

15. The method of claim 14, wherein the temperature is between approximately 350 degrees Celsius and approximately 500 degrees Celsius.

16. The method of claim 15, wherein the temperature is between approximately 425 degrees Celsius and approximately 475 degrees Celsius and wherein the period of time is between approximately 20 seconds and approximately 40 seconds.

17. The method of claim 16, wherein the temperature is approximately 450 degrees Celsius and wherein the period of time is approximately 30 seconds.

20. The method of claim 11, wherein the bonding pad comprises aluminum.

21. The method of claim 13, wherein the first adhesion sublayer comprises titanium tungsten (TiW), the barrier sublayer comprises titanium tungsten nitride (TiWN), and the second adhesion sublayer comprises titanium tungsten (TiW).

22. A method for use in semiconductor device fabrication comprising the steps of:

(a) forming over a semiconductor substrate a semiconductor device having a bonding pad;

(b) forming over the semiconductor device a passivation layer having an opening which exposes a portion of the bonding pad;

(c) probing the bonding pad to test the semiconductor device;

(d) forming, after the probing step (c), a barrier layer over the exposed portion of the probed bonding pad;

(e) forming a bump comprising gold over the barrier layer;

(f) annealing the bump with a rapid thermal anneal by heating the bump at a temperature between approximately 425 degrees Celsius and approximately 475 degrees Celsius for a period of time between approximately 20 seconds and approximately 40 seconds; and

(g) forming an interconnection between the bump and a semiconductor package.

23. The method of claim 22, wherein the barrier layer forming step (d) comprises the steps of:

(i) forming a first adhesion sublayer over the exposed portion of the probed bonding pad,

(ii) forming a barrier sublayer over the first adhesion sublayer, and

(iii) forming a second adhesion sublayer over the barrier sublayer.

24. The method of claim 23, wherein the bonding pad comprises aluminum (Al), the first adhesion sublayer comprises titanium tungsten (TiW), the barrier sublayer comprises titanium tungsten nitride (TiWN), and the second adhesion sublayer comprises titanium tungsten (TiW).

25. The method of claim 22, wherein the bump forming step (e) comprises the steps of:

(i) forming over the barrier layer a patterned layer having an opening over the exposed portion of the bonding pad, and

(ii) using a plating process to form in the opening of the patterned layer the bump comprising gold.

26. The method of claim 22, wherein the temperature is approximately 450 degrees Celsius and the period of time is approximately 30 seconds.

27. The method of claim 22, wherein the forming step (g) includes the step of using a tape automated bonding process.