Vertical power mosfet having thick metal layer to reduce distributed resistance
First Claim
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1. A vertical power transistor comprising:
- a die comprising a semiconductor material;
a plurality of transistor cells arrayed on said die, each of said cells containing a first region located near a surface of said die and a control element and being arranged so as to permit a current to flow between said first region and a second region located at a position separated from said surface, the magnitude of said current being controlled by an electrical signal applied to said control element;
a thin metal layer in electrical contact with said first region of each of said cells;
a thick metal layer formed in electrical contact with said thin metal layer so as to form a low-resistance path between said first region of each of said cells; and
a passivation layer overlying a portion of a top surface of said die, said passivation layer abutting a lateral edge of said thick metal layer but not overlapping a top surface of said thick metal layer, at least a portion of a top surface of said passivation layer remaining uncovered.
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Abstract
The on-resistance of a vertical power transistor is substantially reduced by forming a thick metal layer on top of the relatively thin metal layer that is conventionally used to make contact with the individual transistor cells in the device. The thick metal layer is preferably plated electrolessly on the thin metal layer through an opening that is formed in the passivation layer.
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Citations
26 Claims
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1. A vertical power transistor comprising:
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a die comprising a semiconductor material; a plurality of transistor cells arrayed on said die, each of said cells containing a first region located near a surface of said die and a control element and being arranged so as to permit a current to flow between said first region and a second region located at a position separated from said surface, the magnitude of said current being controlled by an electrical signal applied to said control element; a thin metal layer in electrical contact with said first region of each of said cells; a thick metal layer formed in electrical contact with said thin metal layer so as to form a low-resistance path between said first region of each of said cells; and a passivation layer overlying a portion of a top surface of said die, said passivation layer abutting a lateral edge of said thick metal layer but not overlapping a top surface of said thick metal layer, at least a portion of a top surface of said passivation layer remaining uncovered. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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Specification