Geometric enhancement of photodiodes for low dark current operation

• US 5,665,998 A
• Filed: 02/14/1996
• Issued: 09/09/1997
• Est. Priority Date: 05/23/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Turner, Arthur M., Forehand, David I., Dreiske, Peter D.
• Primary Examiner(s): Ngo, Ngan V.
• Assistant Examiner(s): Wilson, Allan R.
• Application Number:
  US08/601,557
• Time in Patent Office: 573 Days
• Field of Search: 257/442, 257/446, 257/461, 257/465, 257/466, 257/438, 257/441, 257/444, 257/445, 257/447, 257/448, 257/458, 257/459, 257/460, 257/462, 257/463, 257/464
• US Class Current: 257/446
• CPC Class Codes: H01L 31/03529 Shape of the potential jump barrier or surface barrier
• CPC Class Codes: H01L 31/1032 the devices comprising active layers formed only by AIIBVI compounds, e.g. HgCdTe IR photodiodes
• CPC Class Codes: Y02E 10/50 Photovoltaic [PV] energy
• CPC Class Codes: Y10S 148/08 Infrared
• CPC Class Codes: Y10S 257/91 Diode arrays, e.g. diode read-only memory array
• CPC Class Codes: Y10S 438/965 Shaped junction formation

Abstract

A substantial portion of the material at the pn junction (27) of the photodiode (37, 41) having an implanted region extending to a surface thereof is selectively removed (39), leaving a very small junction region (35, 43) with the remainder of the p-type (23) and n-type (25) material of each photodiode being spaced apart or electrically isolated at what was originally the junction. In the ion implanted n-type on p-type approach, the majority of the signal is created in the implanted n-type region while the majority of the noise is generated in the p-type region. By selectively removing p-type material, n-type material or both from the pn junction of the diode or otherwise electrically isolating most of the p-type and n-type regions from each other at the pn junction and thereby minimizing the pn junction area, noise is greatly reduced without affecting the signal response of the photodiode. With this approach, the present implant technology can still be used with the achievement of high temperature operational capability above 77° Kelvin and up to about 110° Kelvin.

Claims

1. A photodiode comprising:

(a) a first region of semiconductor material of predetermined conductivity type; and

(b) a second region of opposite conductivity type surrounded by said first region so that exterior portions thereof oppose exterior portions of said first region and spaced from said first region along a major portion of the second region opposing said first region, the remainder of said second region opposing said first region forming a semiconductor junction with said first region.

2. The photodiode of claim 1 wherein said second region extends to a surface of said first region.

3. The photodiode of claim 1 wherein said second region extends to each of a pair of opposing surfaces of said first region.

4. The photodiode of claim 2 wherein said second region extends to each of a pair of opposing surfaces of said first region.

5. The photodiode of claim 1 wherein said first region is p-type and said second region is n-type.

6. The photodiode of claim 4 wherein said first region is p-type and said second region is n-type.

7. The photodiode of claim 1 wherein said semiconductor material is taken from the group consisting of group II-VI compounds, group III-V compounds, silicon, and germanium.

8. The photodiode of claim 2 wherein said semiconductor material is taken from the group consisting of group II-VI compounds, group III-V compounds, silicon and germanium.

9. The photodiode of claim 1 wherein said semiconductor material is HgCdTe.

10. The photodiode of claim 2 wherein said semiconductor material is HgCdTe.

11. A focal plane array comprising:

(a) a substrate containing an electrical circuit therein; and

(b) a photodiode array secured to said substrate and electrically coupled to said substrate, said diode array comprising a plurality of photodiodes, each of said photodiodes including;

(i) a first region of semiconductor material of predetermined conductivity type; and

(ii) a second region of opposite conductivity type surrounded by said first region so that exterior portions thereof oppose exterior portions of said first region and spaced from said first region along a major portion of the second region opposing said first region, the remainder of said second region opposing said first region forming a semiconductor junction with said first region.

12. The array of claim 11 wherein said second region extends to a surface of said first region.

13. The array of claim 11 wherein said second region extends to each of a pair of opposing surfaces of said first region.

14. The array of claim 12 wherein said second region extends to each of a pair of opposing surfaces of said first region.

15. The array of claim 11 wherein said first region is p-type and said second region is n-type.

16. The array of claim 14 wherein said first region is p-type and said second region is n-type.

17. The array of claim 11 wherein said semiconductor material is taken from the group consisting of group II-VI compounds, group III-V compounds, silicon and germanium.

18. The array of claim 16 wherein said semiconductor material is taken from the group consisting of group II-VI compounds, group III-V compounds, silicon and germanium.

19. The array of claim 11 wherein said semiconductor material is HgCdTe.

20. The array of claim 18 wherein said semiconductor material is HgCdTe.