Programmable impedance output driver

• US 5,666,078 A
• Filed: 02/07/1996
• Issued: 09/09/1997
• Est. Priority Date: 02/07/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Schneiderwind, Michael J., Pilo, Harold, Lamphier, Steven H., Towler, Fred J.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): TON, MY TRANG
• Application Number:
  US08/597,655
• Time in Patent Office: 580 Days
• Field of Search: 327/63, 327/64, 327/108, 327/109, 327/111, 327/112, 327/210, 327/211, 327/212, 326/30, 326/37, 326/40, 326/49, 326/50, 326/82, 326/83, 326/86
• US Class Current: 327/108
• CPC Class Codes: H03K 19/018585 programmable

Abstract

An output driver circuit is disclosed that generates an accurate and predictable output impedance driver value corresponding to a programmable external impedance. The output driver circuit includes an external resistance device, voltage comparator device, control logic, an evaluate circuit and off-chip driver (OCD) circuit. Voltage from the external resistance device (VZQ) is compared with voltage created from the evaluate circuit (VEVAL) by the voltage comparator device, which indicates to the control logic whether VEVAL is greater than or less than VZQ. The control logic will adjust the evaluate circuit accordingly with a count until the two voltages are basically equal (i.e., the count is alternating between two adjacent binary count values). At which time the control logic operates the OCD with the lower of the two adjacent count values to produce a proper and predictable driving impedance.

Claims

1. An output driver circuit, comprising:

an external resistance device for programming a desired impedance into said output driver circuit;

a voltage comparative device, coupled to said extreme resistance device, for comparing a voltage of said desired impedance with an evaluate voltage and generating a signal indicating which of said voltages is higher;

a control logic device, coupled to said voltage comparative device, for receiving said signal and generating a first and second count from said signal, wherein said second count corresponds to a prior first count;

an evaluate device, coupled to said control logic device and said voltage comparative device, for receiving said first count and modifying said evaluate voltage with said first count to more closely resemble said voltage of said desired impedance;

a low select device, coupled to said control logic device, for receiving said first and second count, and selecting and outputting the lowest of said first and second count; and

an output device, coupled to said low select device, for receiving said output of said low select device and generating an output impedance corresponding to said output of said low select device.

2. The circuit of claim 1, wherein said evaluate device further comprises:

binary-weighted transistors, wherein each of said transistors receive a bit value from said first count and is turned off or on according to said bit value.

3. The circuit of claim 1, further comprising:

a clock generator device, coupled to said voltage comparator device and said evaluate device, for placing said voltage comparator device and said evaluate device in a standby phase for a desired amount of time, wherein no current dissipates in said circuit during said standby phase.

4. A method for matching a desired impedance with an output impedance of an output driver circuit comprising the steps of:

a) programming said desired impedance into said output driver circuit;

b) comparing a voltage of said desired impedance with an evaluate voltage and generating a signal indicating which of said voltages is higher;

c) generating a first and second count from said signal, wherein said second count corresponds to a prior first count;

d) modifying said evaluate voltage with said first count to more closely resemble said voltage of said desired impedance;

e) selecting and outputting the lowest of said first and second count; and

f) generating an output impedance corresponding to said output of said lowest of said first and second count.

5. The method of claim 4, wherein said modifying step further comprises the step of:

providing binary-weighted transistors, wherein each of said transistors receive a bit value from said first count and is turned off or on according to said bit value.

6. The method of claim 4, further comprising the step of:

placing said output driver circuit in a standby phase for a desired amount of time, wherein no current dissipates in said circuit during said standby phase.

7. A system having an output driver circuit, said system comprising:

an external resistance device for programming a desired impedance into said output driver circuit;

a voltage comparative device, coupled to said external resistance device, for comparing a voltage of said desired impedance with an evaluate voltage and generating a signal indicating which of said voltages is higher;

a control logic device, coupled to said voltage comparative device, for receiving said signal and generating a first and second count from said signal, wherein said second count corresponds to a prior first count;

an evaluate device, coupled to said control logic device and said voltage comparative device, for receiving said first count and modifying said evaluate voltage with said first count to more closely resemble said voltage of said desired impedance;

a low select device, coupled to said control logic device, for receiving said first and second count, and selecting and outputting the lowest of said first and second count; and

an output device, coupled to said low select device, for receiving said output of said low select device and generating an output impedance corresponding to said output of said low select device.

8. The system of claim 7, wherein said evaluate device further comprises:

binary-weighted transistors, wherein each of said transistors receive a bit value from said first count and is turned off or on according to said bit value.

9. The system of claim 7, further comprising:

a clock generator device, coupled to said voltage comparator device and said evaluate device, for placing said voltage comparator device and said evaluate device in a standby phase for a desired amount of time, wherein no current dissipates in said circuit during said standby phase.