Semiconductor memory device with complete inhibition of boosting of word line drive signal and method thereof

• US 5,666,313 A
• Filed: 09/04/1996
• Issued: 09/09/1997
• Est. Priority Date: 11/29/1991
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Ichiguchi, Tetsuichiro
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Tran, Andrew Q.
• Application Number:
  US08/707,364
• Time in Patent Office: 370 Days
• Field of Search: 365/189.09, 365/189.11, 365/204, 365/226, 365/230.06, 365/195, 307/272.3, 307/296.3, 307/482, 307/578, 327/142, 327/143
• US Class Current: 365/195
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A word line drive signal generating circuit, which generates a word line drive signal RX to a selected word line, includes an RX generating circuit responsive to an external row address strobe signal *RAS (or/RAS) for generating word line drive signal RX, a determination circuit responsive to an operating power supply voltage level or an externally applied signal for determining whether the word line drive signal RX should be boosted up, and a boosting circuit responsive to the word line drive signal RX and an output of determination circuit for boosting up the word line drive signal RX. The word line drive signal RX is boosted up to or above the operating power supply voltage level only when the determination circuit determines it to be necessary. Thereby, a high voltage is not normally applied to the word line, so that deterioration of breakdown voltage of the word line is prevented, and the reliability of the word line is improved.

Claims

1. A semiconductor memory device including a plurality of word lines each having a row of memory cells connected thereto, comprising:

word line drive signal generating means for generating a word line drive signal to be transferred onto a selected word line;

determination means responsive to a signal other than said word line drive signal for determining whether the word line drive signal should be completely inhibited from being boosted up; and

boosting means responsive to said determination means for selectively boosting up the word line drive signal, wherein

said determination means includes;

detecting means for detecting a level of potential supplied from an operating power supply of the semiconductor memory device, and

decision means responsive to said detecting means for completely inhibiting the boosting up by said boosting means when the potential level is detected to be above a predetermined level.

2. A method of operating a semiconductor memory device including a plurality of word lines having memory cells connected thereto, comprising the steps of:

generating a word line drive signal to be transferred onto a selected word line at a first timing;

determining whether or not the word line drive signal should be further boosted up, in response to an indication other than said word line driving signal, and

selectively boosting further up the word line drive signal, according to a result of determination in said step of determining, said step of determining including the steps of detecting a potential level of an operating power supply of the semiconductor memory device, and determining that the boosting up operation should not be effected when said potential level is above a predetermined potential level, to completely inhibit said boosting.