Data detection apparatus

• US 5,666,341 A
• Filed: 09/13/1996
• Issued: 09/09/1997
• Est. Priority Date: 09/18/1995
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Miyachi, Hiroyuki, Ishibashi, Hiromiti, Horibe, Ryusuke, Shimada, Toshiyuki
• Primary Examiner(s): HUBER, PAUL W
• Application Number:
  US08/710,266
• Time in Patent Office: 361 Days
• Field of Search: 369/47, 369/48, 369/49, 369/53, 369/54, 369/59, 369/60, 369/124, 360/27, 360/29, 360/30, 360/32, 360/39, 360/51
• US Class Current: 369/47.28
• CPC Class Codes: G11B 19/12 by sensing distinguishing features of or on records, e.g. diameter end mark
• CPC Class Codes: G11B 20/1403 characterised by the use of two levels
• CPC Class Codes: G11B 27/3027 used signal is digitally coded
• CPC Class Codes: H03L 7/081 provided with an additional controlled phase shifter H03L7/0998 takes precedence
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/113 using frequency discriminator

Abstract

A reproduced signal is digitized so as to count a time interval of a specified pattern simultaneously with the count of a clock period of a phase lock loop circuit. A phase lock loop clock frequency is subjected to a feedback control based on the information indicated the difference between the time interval and the clock period. In this manner, a frequency loop performs a feedback operation so that a frequency of the reproduced signal falls within a capture range of a phase lock-in, thereby increasing the speed of phase lock-in.

Claims

1. An apparatus for reproducing digital information which is subjected to modulation recording with a discrete record length, comprising:

a digitizing section for digitizing a reproduced signal at a predetermined level so as to output a digital signal;

an oscillator for outputting a clock signal having a frequency proportional to an input signal;

a phase comparing section for comparing the digital signal with the clock signal so as to output a first difference signal indicating a difference in phase between the digital signal and the clock signal;

a specified pattern width detecting section for detecting a time interval of a specified pattern included in the digital signal so as to output first information indicating either a reproduced period or a reproduced frequency;

an oscillating period detecting section for detecting a period of the clock signal so as to output second information indicating either an oscillating period or an oscillating frequency of the oscillator;

a period comparing section for comparing the first information with the second information so as to output a second difference signal indicating a difference between the first information and the second information;

an operating section for performing an operation in accordance with the first difference signal and the second difference signal; and

a filter for limiting a frequency band of the output from the operating section so as to output a resultant signal as an input signal for oscillator;

wherein the apparatus has;

a phase lock loop operating so that the clock signal is phase-locked with an edge of the digital signal by the oscillator, the phase comparing section, the operating section and the filter; and

a frequency loop operating so that a clock period and reproducing period become almost identical to each other by the oscillator, the specified pattern width detecting section, the oscillating period detecting section, the period comparing section, the operating section and the filter.

2. An apparatus according to claim 1, wherein the specified pattern width detecting section counts the time interval of the specified pattern included in the digital signal with a fixed clock.

3. An apparatus according to claim 1, wherein the oscillating period detecting section counts a period of n cycles of the clock signal with a fixed clock, where n is a natural number.

4. An apparatus according to claim 1, wherein the operating section is a voltage generator for receiving the first difference signal and the second difference signal so as to output a voltage in accordance therewith.

5. An apparatus according to claim 1, wherein the operating section is a charge pump section for receiving the first difference signal and the second difference signal so as to discharge or absorb a current in accordance therewith.

6. An apparatus according to claim 5, wherein the charge pump section includes an adder for receiving the first difference signal and the second difference signal so as to output a logical OR signal of the first and second difference signals, and a charge pump for discharging or absorbing a current in accordance with the logical OR signal.

7. An apparatus according to claim 5, wherein the charge pump section includes a first charge pump for discharging or absorbing a current having a first value in accordance with the first difference signal and a second charge pump for discharging or absorbing a current having a second value in accordance with the second difference signal.

8. An apparatus according to claim 5, wherein the charge pump section includes a first hold control input for inhibiting a discharging and absorbing operation of a current in accordance with the first difference signal so as to stop a phase lock loop, a second hold control input for inhibiting a discharging and absorbing operation of a current in accordance with the second difference signal so as to stop a frequency loop, and a loop controller for outputting a control signal to the fist hold control input and the second hold control input.

9. An apparatus according to claim 3, wherein the oscillating period detecting section counts a period of n cycles of the clock signal with a clock having a 1k frequency of the fixed clock, where n and k each is a natural number.

10. An apparatus according to claim 8, further comprising a synchronization detecting for detecting a phase locked state between the clock signal and the digital signal so as to output a synchronization detection signal,

wherein the loop controller operates the phase lock loop and the frequency loop in accordance with the synchronization detection signal.

11. An apparatus according to claim 10, wherein the synchronization detecting section detects that a value obtained by integrating an absolute value of the first difference signal is at a level equal to or lower than a prescribed level.

12. An apparatus according to claim 8, wherein the loop controller receives the second difference signal so as to control the phase lock loop and the frequency loop in accordance with the second difference signal.

13. An apparatus according to claim 8, further comprising a synchronization section for receiving the digital signal and the clock signal so as to output reproduced data in which the digital signal is synchronized with the clock signal and a pattern detecting section for receiving the clock signal and the reproduced signal so as to detect the presence of a periodic pattern periodically included in the reproduced data and whether the pattern has a periodicity,

wherein the loop controller receives a signal output from the pattern detecting section so as to operate the phase lock loop and the frequency loop in accordance with the signal.

14. An apparatus according to claim 8, further comprising a synchronization detecting section for detecting a phase locked state between the clock signal and the digital signal so as to output a synchronization detection signal, a synchronizing section for receiving the digital signal and the clock signal so as to output reproduced data in which the digital signal is synchronized with the clock signal, and a pattern detecting section for receiving the clock signal and the reproduced signal so as to detect the presence of a periodic pattern periodically included in the reproduced data and whether the pattern has a periodicity,

wherein the loop controller receives a signal output from the pattern detecting section so as to operate the phase lock loop and the frequency loop in accordance with the signal.

15. An apparatus according to claim 8, further comprising:

a synchronization section for receiving the digital signal and the clock signal so as to output reproduced data synchronized with the clock signal; and

a pattern detecting section for receiving the clock signal and the reproduced data so as to detect the presence of a periodic pattern periodically included in the reproduced data,

wherein the loop controller receives the second difference signal and a signal output from the pattern detecting section so as to operate the phase lock loop and the frequency loop in accordance therewith.

16. An apparatus according to claim 8, further comprising a synchronization detecting section for detecting a phase locked state between the clock signal and the digital signal so as to output a synchronization detecting signal,

wherein the loop controller receives the second difference signal and the synchronization detecting signal so as to operate the phase lock loop and the frequency loop in accordance therewith.

17. An apparatus according to claim 8, further comprising:

a synchronization detecting section for detecting a phase locked state between the clock signal and the digital signal so as to output a synchronization detecting signal;

a synchronization section for receiving the digital signal and the clock signal so as to output reproduced data in which the digital signal is synchronized with the clock signal; and

a pattern detecting section for receiving the clock signal and the reproduced data so as to detect the presence of a periodic pattern periodically included in the reproduced data and whether the pattern has a periodicity,

wherein the loop controller receives the second difference signal, the synchronization detecting signal and an output from the pattern detecting section so as to operate the phase lock loop and the frequency loop in accordance therewith.

18. An apparatus according to claim 17, wherein the loop controller receives the synchronization detecting signal or a signal output from the pattern detecting section as a second hold control input for the charge pump section and receives the second difference signal as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate until the second difference signal falls within a prescribed range, both the phase lock loop and the frequency loop are operated when the second difference signal falls within the prescribed range, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when a periodic pattern is detected by the synchronization detecting signal or the pattern detecting section.

19. An apparatus according to claim 17, wherein the loop controller receives the synchronization detecting signal or a signal output from the pattern detecting section as a second hold control input for the charge pump section and receives the second difference signal as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate until the second difference signal falls within a prescribed range, both the phase lock loop and the frequency loop are operated when the second difference signal falls within the prescribed range, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when a phase locked state is detected by the synchronization detecting signal or a periodic pattern is detected by the pattern detecting section, and both the phase lock loop and the frequency loop are operated when the phase locked state or the periodic pattern is not detected by the synchronization detecting signal any more.

20. An apparatus according to claim 17, wherein the loop controller receives the synchronization detecting signal or the output from the pattern detection section as a second hold control input for the charge pump section and receives the second difference signal as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate until the second difference signal falls within a prescribed range, both the phase lock loop and the frequency loop are operated when the first difference signal falls within the prescribed range, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when a periodic pattern is detected by the synchronization detecting signal or the pattern detecting section, and both the phase lock loop and the frequency loop are operated when the phase locked state is not detected by the synchronization detecting signal or the periodic pattern is not detected by the pattern detecting section.

21. An apparatus according to claim 14, wherein the loop controller receives the synchronization detecting signal or a signal output from the pattern detection section as a second hold control input for the charge pump section and receives a tracking on signal of a disk drive as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate in a tracking off state, both the phase lock loop and the frequency loop are operated in a tracking on state, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when the phase locked state is detected by the synchronization detecting signal or a periodic pattern is detected by the pattern detecting section.

22. An apparatus according to claim 14, wherein the loop controller receives the synchronization detecting signal or the signal output from the pattern detection section as a second hold control input for the charge pump section and receives a tracking on signal of a disk drive as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate in a tracking off state, both the phase lock loop and the frequency loop are operated in a tracking on state, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when the phase locked state is detected by the lock detecting signal or a periodic patter is detected by the pattern detecting section, and the phase lock loop and the frequency loop are operated when the periodic pattern is not detected.

23. An apparatus according to claim 14, wherein the loop controller receives the synchronization detecting signal or the signal output from the pattern detection section as a second hold control input for the charge pump section and receives a tracking on signal of a disk drive as a first hold control input for the charge pump section,

wherein, upon a phase lock-in, the phase lock loop is inhibited from operating while still allowing the frequency loop to operate in a tracking off state, both the phase lock loop and the frequency loop are operated in a tracking on state, and the frequency loop is inhibited from operating while allowing the phase lock loop to operate when a phase locked state is detected by the synchronization detecting signal or a periodic pattern is detected by the pattern detecting section, and the phase lock loop is inhibited from operating while allowing the frequency loop to operate when the periodic pattern is not detected by the pattern detecting section any more.

24. An apparatus according to claim 5, wherein the charge pump section discharges or absorbs a predetermined current for a predetermined time in accordance with a polarity of the second difference signal output from the period comparing section for each predetermined period.

25. An apparatus according to claim 5, wherein the charge pump section outputs a current for a predetermined time proportional to the second difference signal output from the period comparing section for each predetermined period.

26. An apparatus according to claim 5, wherein the charge pump section discharges or absorbs a predetermined current for a predetermined time in accordance with a polarity of the second difference signal output from the period comparing section for each predetermined period under control at a time interval proportional to an absolute value of the second difference signal.

27. An apparatus according to claim 1, wherein the phase comparing section includes:

a period detector for outputting a signal proportional to an oscillating period of the oscillator;

a delay circuit for delaying the digital signal proportional to an output from the period detecting section;

a pulse gate circuit for outputting clock edge information of an oscillating output from the oscillator only hen the digital signal is input;

an phase difference detector for comparing a phase of an output from the delay circuit and a phase of the output from the pulse gate circuit so as to generate two pulse representative of positive or negative in accordance with whether a phase difference is plus or minus with a pulse width in accordance with the amount of the phase difference, and

wherein the amount of delay of the delay circuit is controlled so as to be proportional to an oscillating period of the oscillator.

28. An apparatus according to claim 27, wherein the amount of delay of the delay circuit is controlled so as to be proportional to the oscillating period of the oscillator and is capable of being held by an external signal.

29. An apparatus according to claim 27, wherein the amount of delay of the delay circuit is controlled so as to be proportional to the oscillating period of the oscillator and is switchable to a prescribed amount of delay by an external signal.

30. An apparatus according to claim 27, wherein the amount of delay of the delay circuit is controlled so as to be proportional to a current or a voltage proportional to the oscillating period of the oscillator which is subjected to low pass filtration.

31. An apparatus according to claim 1, wherein the phase comparing section includes:

a digital-analog convertor for outputting a current or a voltage proportional to a count value of the specified pattern width detecting section;

a delay circuit for providing the amount of delay proportional to an output from the digital to analog convertor;

a pulse gate circuit for outputting clock edge information serving as an output of the oscillator only when the digital signal is input; and

a phase difference detector for comparing a phase of an output from the delay circuit and a phase of the output from the pulse gate circuit so as to generate two pulses, which are representative of positive or negative in accordance with whether a phase difference is plus or minus, with a pulse width in accordance with the amount of the phase difference, and

wherein the amount of delay of the delay circuit is controlled proportional to a count value of the specified pattern width detecting section.