Power consumption control method and apparatus for a communication system subscriber unit

• US 5,666,355 A
• Filed: 03/26/1996
• Issued: 09/09/1997
• Est. Priority Date: 07/21/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Vessal, David, Kinney, Kevin, Vanderslice, William T. Jr., Huah, Jim J., Lemmo, Mark A., Regensburg, Michael W., Kaewell, John
• Primary Examiner(s): Kizou, Hassan
• Application Number:
  US08/624,703
• Time in Patent Office: 532 Days
• Field of Search: 370/311, 370/321, 370/326, 370/336, 370/337, 370/347, 370/465, 370/498, 379/58, 379/59, 379/61, 455/38.3, 455/343, 340/825.44, 340/311.1
• US Class Current: 370/311
• CPC Class Codes: H04B 1/036 Cooling arrangements
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04B 1/40 Circuits
• CPC Class Codes: H04M 1/73 Battery saving arrangements
• CPC Class Codes: H04M 19/02 providing ringing current or supervisory tones, e.g. dialling tone or busy tone
• CPC Class Codes: H04W 52/0235 where the received signal is a power saving command
• CPC Class Codes: H04W 52/0283 with sequential power up or power down of successive circuit blocks, e.g. switching on the local oscillator before RF or mixer stages
• CPC Class Codes: H04W 52/029 reducing the clock frequency of the controller
• CPC Class Codes: H04W 52/0293 having a sub-controller with a low clock frequency switching on and off a main controller with a high clock frequency
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A subscriber unit of a time division multiple access (TDMA) radiotelephone system is, from a power consumption standpoint, reconfigured in each time slot of a TDMA frame to a power consumption tessellation in which subscriber unit circuit components not needed for communication signal processing in that time slot are powered down, and other components are powered up. Some circuit components are powered down by switching their power supply circuits. In order to minimize the extent of circuitry that must be provided to distribute power consumption control signals, other techniques (which utilize circuitry provided for other purposes), such as clock frequency control or power down commands, also are utilized to modify controlled circuit component power consumption without actually controlling power supply circuits. Loop connection length between the subscriber unit and the subscriber'"'"'s telephone set, or other terminal equipment, is limited to a length which is much less than the length of a radio link on which the subscriber unit operates. Programmable ring frequency logic controls the frequency of a ringing signal generator, and a high frequency ring control signals switched on and off in the cadence of ringing operation. Also an expansion header is provided to enable serving plural subscriber loop circuits with the same radio equipment for reducing per line power consumption.

Claims

1. A method for operating a TDMA radio subscriber unit to conserve power, said subscriber unit comprising a plurality of cooperatively connected circuit components, said subscriber unit (a) operating in different signal processing states at different times, and (b) operating within a plurality of time slots of a recurring time frame, said method comprising the steps of:

identifying for each of said states, respective ones of said circuit components not required to be powered at a first power consumption level for said TDMA radio subscriber unit to operate;

assigning to said respective ones of said circuit components a second power consumption level, lower than said first power consumption level, for said each of said states;

transitioning said subscriber unit between two of said signal processing states responsive to a transition between two of said plurality of time slots; and

operating each of said circuit components at one of said first power consumption level and said second power consumption level depending on whether said each of said circuit components has been assigned said second power level for any one of said states within said one of said time slots said subscriber unit is operating within.

2. The method in accordance with claim 1 in which said operating step comprises:

switching open and closed a power supply lead of at least one of said circuit components to change the power consumption level of said at least one of said circuit components.

3. The method in accordance with claim 1 in which a first portion of said plurality of circuit components is connected in a transmit signal path including baseband, IF, and RF sections and a second portion of said circuit components are connected in a receive signal path including RF, IF, and baseband sections, and said operating step comprises further:

in each time interval when at least said receive path IF section is operating at said first power consumption level, controlling at least one of said transmit path circuit components in said IF section thereof also to operate at approximately its first power consumption level.

4. The method in accordance with claim 1 in which a first portion of said plurality of circuit components are connected in a transmit signal path including baseband, IF, and RF sections and a second portion of said circuit components are connected in a receive signal path including RF, IF, and baseband sections, a digital signal processor is included in both of said transmit and receive signal paths, and said operating step comprises further:

controlling said digital signal processor to operate at its reduced power consumption level during at least a part of every time frame in which either of said transmit and receive signal paths is operated at their first power consumption level.

5. The method in accordance with claim 1 in which a first portion of said plurality of circuit components are connected in a transmit signal path including baseband, IF, and RF sections and a second portion of said circuit components are connected in a receive signal path including RF, IF, and baseband sections, at least a portion of said IF sections operates in a clocked digital signal mode in response to clock signals supplied thereto, and said operating step comprises further:

controlling power consumption level in at least said portion of said IF sections to be at said first power consumption level or said second power consumption level by turning said clocking signals on and off.

6. The method in accordance with claim 1 in which at least one of said circuit components is a CMOS circuit and is clocked at a first predetermined rate to switch between at least a first activity state and a second activity state and said operating step comprises:

reducing the rate of clocking of said at least one of said circuit components from said first predetermined rate for thereby reducing the frequency of switching between activity states and thereby reducing power consumed by said at least one of said circuit components.

7. The method in accordance with claim 1, further comprising the step of transitioning said subscriber unit between two of said signal processing states responsive to detecting said subscriber unit entering into one of an off-hook state, an on-hook state and a ring state.

8. In a TDMA radiotelephone system subscriber unit including a plurality of cooperatively interconnected circuit components which each change power consumption level between a) a first level for communication signal processing and b) a predetermined reduced second level, a method for reducing power consumption in said subscriber unit comprising the steps of:

during each of a plurality of TDMA time slots, maintaining at said second level ones of said plurality of circuit components which are not required for signal processing in said each of said plurality of TDMA time slots if said subscriber unit is in one of a plurality of predetermined states in which said subscriber unit operates during said each of said plurality of TDMA time slots;

during said each of said plurality of TDMA time slots maintaining at said first level others of said circuit components, which are required for communication signal processing in said each of said plurality of TDMA time slots, to power such circuit components to their respective signal processing power consumption levels if said subscriber unit is in one of said plurality of predetermined states in which said subscriber unit operates during said each of said plurality of TDMA time slots; and

transitioning said subscriber unit between two of said plurality of states responsive to a transition between two of said plurality of TDMA time slots.

9. A subscriber unit for coupling a subscriber loop circuit to a radio communication link in a time division multiple access (TDMA) radio telecommunication system, said subscriber unit comprising:

plural cooperatively connected circuit components for at least one of reception and transmission signal processing, when electrically powered, in recurring time division frames, each frame comprising a predetermined number of time slots;

means for connecting electrical power to said subscriber unit to supply power consumption needs of said circuit components;

means for transitioning said subscriber unit between two of said plurality of predetermined states responsive to a transition between two of said plurality of time slots; and

means for limiting power consumed by a predetermined plurality of said subscriber unit circuit components during each of said time slots to that which is needed by said components, respectively, during said each of said time slots for said signal processing if said subscriber unit is in one of a plurality of predetermined states in which said subscriber unit operates during said each of said time slots.

10. The subscriber unit in accordance with claim 9 in which said subscriber loop circuit includes a subscriber communication instrument and in which:

said components include means for interfacing said subscriber unit with said subscriber loop circuit for analog signals, said interfacing means comprising means for connecting a power supply of a first predetermined voltage to said interfacing means, and means for providing to said loop circuit a substantially constant current of predetermined value at a second predetermined voltage at least partly determined by the length of said subscriber loop circuit and which second predetermined voltage is less than said first predetermined voltage, said providing means consuming substantially constant power regardless of the value of said second predetermined voltage, and

the length of said subscriber loop circuit between said subscriber unit and said communication instrument is less than the length of said radio link.

11. The subscriber unit in accordance with claim 9 in which said limiting means comprises:

means, operative during each time slot, for powering each of said circuit components at either a first predetermined level for participation in said signal processing or a second lower predetermined level for standby operation in which circuit component is insufficiently energized for participation in said signal processing.

12. The subscriber unit in accordance with claim 11 in which:

at least one of said circuit components is an amplification circuit receiving power through a series electric current carrying circuit; and

said powering means comprises switching means connected in series in said current carrying circuit, and

means for operating said switching means to open said electric current carrying circuit in respective ones of said time slots when said at least one of said circuit components is not required for participation in said signal progressing.

13. The subscriber unit in accordance with claim 11 in which:

at least one of said circuit components is an amplification circuit having a bias current input connection; and

said powering means comprises a switchable constant-current source connected to supply current to said bias current input connection, and

means for operating said switchable constant-current source to reduce said current in respective ones of said time slots when said at least one of said circuit components is not required for participation in said signal processing.

14. The subscriber unit in accordance with claim 11 in which:

at least one of said circuit components is a clocked signal processing circuit comprising semiconductor circuitry which consumes substantially less power when it is not being clocked than it does when it is clocked; and

said powering means comprises means for interrupting the clocking of said clocked signal processing circuit in respective ones of said, time slots when it is not required for participation in said signal processing.

15. The subscriber unit in accordance with claim 11 in which:

at least one of said circuit components is an integrated circuit chip having an included powering down mode of operation; and

said powering means comprises means for activating said powering down mode in respective ones of said time slots when said at least one circuit component is not required for participation in said signal processing.

16. The subscriber unit in accordance with claim 9 in which:

at least one of said circuit components is an amplification circuit in which power consumption is approximately proportional to the amplitude of signals being amplified, said amplification circuit having an input port to which signals to be amplified are applied;

another of said circuit components is connected in a signal processing path to provide signals to said amplification circuit input port for amplification; and

said limiting means comprises means in said another circuit for reducing the amplitude of said signals provided to said amplification circuit input port in selected time slots and thereby powering down said amplification circuit.

17. The subscriber unit in accordance with claim 9 in which:

at least one of said circuit components is a line interface unit connected in a baseband section of said subscriber unit for interfacing said subscriber unit with said subscriber loop circuit,

said subscriber unit includes a digital signal processor (DSP) for controlling cooperative operation of said circuit components, data and address buses extending between said DSP and at least some of said circuit components for effecting that control, and a first communication signal interface circuit between said DSP and said line interface unit,

an expansion header is provided for plug-in accommodation of a circuit card including circuitry interfacing with another subscriber loop circuit, said expansion header having a power supply connection, means are provided for connecting said data and address buses to said expansion header, and

a second communication signal interface circuit is connected between said DSP and said expansion header.

18. The subscriber unit in accordance with claim 9 in which said circuit components include:

means for supplying a clock signal of a predetermined frequency,

a digital signal processor including producing means for producing a data word representing a selectable one frequency of a plurality of predetermined ringing frequencies,

means responsive to said data word and said clock signal, for generating a low amplitude signal at said selectable one frequency, means, responsive to said clock signal, for producing a signal having an amplitude larger than the amplitude of said selectable one frequency and having a frequency greater that the frequency of said selectable one frequency, said larger amplitude signal having both positive and negative polarity portions in each frequency cycle,

means for half-wave rectifying separately each of said positive and negative polarity portions,

means, responsive to said selectable one frequency, for alternately sampling said separately rectified positive and negative polarity portions, and

means for low pass filtering an output of said sampling means to produce a ringing signal at said larger amplitude and at said selectable one frequency.

19. The subscriber unit in accordance with claim 18 in which

gating means are provided for selectively coupling said clock signal to said producing means and selectively coupling a frequency signal corresponding to said selectable one frequency to said alternately sampling means for periodically powering down said ringing signal generator at a frequency which is less than the frequency of said selectable one frequency during ringing signal production.

20. The subscriber unit in accordance with claim 9 in which one of said components is an analog to digital converter having a multibit bi-directional output port and having means, responsive to a power consumption level control command received at said output port, for controlling power consumption level of said converter, and said limiting means comprises:

means for providing a power-up command and a power-down command;

means for producing an enabling signal at the beginning and end of a predetermined one of said time slots; and

means responsive to said enabling signal, for coupling said power-up command to said converter output port just prior to the beginning of said predetermined one of said time slots and coupling said power-down command to said converter output port just after the end of said predetermined one of said time slots.

21. The subscriber unit in accordance with claim 9 in which:

said subscriber loop circuit includes a communication instrument;

said circuit components include control logic and a digital signal processor;

said digital signal processor includes means responsive to its execution of an idle state instruction both to output a notice signal notifying said control logic means that it is powering down and to power itself down to a level at which it at least retains processing state information and can respond to at least predetermined interrupt signals, said notice signal including a value representing the duration of a digital signal processor powered down interval after which said digital signal processor is to be powered up again; and

said control logic means includes means, responsive to said notice signal, for detecting reception of a change in hook state of said communication instrument,

means for timing said interval after said notice signal is received, and

means for sending a wake-up interrupt signal to said digital signal processor either upon detecting said change in hook stage or upon the timing out of said interval.

22. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among at least predetermined off-hook, on-hook, and ringing functions,

said circuit components include a digital signal processor, means for interfacing said subscriber unit with said subscriber loop circuit for analog signals, and means for converting analog signals from said interfacing means to baseband digital signals provided to said digital signal processor and converting baseband digital signals from said processor to analog signals provided to said interfacing means, and

said limiting means comprises means in said digital signal processor for providing power down command signals to said converting means during all time slots of operation except those in said off-hook function of said subscriber unit and to said interfacing means in all time slots of operation except those in said off-hook function and in transmit and receive time slots of said ringing function.

23. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among at least predetermined loopback, on-hook, ringing, and off-hook functions, each of said on-hook, ringing, and off-hook functions including at least one time slot per frame of signal processing for reception,

said components include a digital signal processor, command signal coupling means, and analog to digital converting means, said converting means having an input connection for receiving analog intermediate frequency signals and having a bi-directional output connection to which it provides corresponding intermediate frequency digital signals, and

said limiting means comprises means in said digital signal processor for providing power down command signals to said output connection by way of said command signal coupling means for powering down said converting means during all time slots of operation except said loopback function, a receiving time slot of said ringing function, and a receiving time slot of said on-hook and off-hook functions.

24. The subscriber unit in a accordance with claim 23 in which said digital signals are in m-bit binary offset format and said processor operates on n-bit 2'"'"'s complement signals, n being larger than m, and means are provided for coupling said digital signals to said digital signal processor comprising:

means for converting said binary offset digital signal to 2'"'"'s complement digital signals,

means for shifting and sign extending said 2'"'"'s complement digital signals to produce n-bit 2'"'"'s complement digital signals, and

means for coupling said n-bit 2'"'"'s complement digital signals from said shifting and sign extending means to said processor.

25. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among predetermined states including a loopback state, an on-hook state, a ringing state, and an off-hook state,

said components include a digital signal processor, command signal coupling means, and clock controlled CMOS digital to analog converting means, said converting means having an input connection for receiving digital intermediate frequency signals and having an output connection to which it provides corresponding analog intermediate frequency signals, and

said limiting means comprises means for producing clock signals of a predetermined frequency, and means for coupling said clock signals to said converting means to enable converting means operation during said loopback state and in time slots in which said subscriber unit is transmitting and is in one of said ringing state and said off-hook state.

26. The subscriber unit in accordance with claim 25 in which said means for coupling clock signals to said converting means comprises:

means for providing at least one clock signal of predetermined frequency,

receiving means for receiving a binary coded multibit word from said digital signal processing means,

a controllable, signal selecting multiplexer having a plurality of input connections, at least one of which is connected to ground,

means, responsive to at least one bit of said multibit word, for controlling said multiplexer to select either said clock signal or ground, and

means for coupling an output of said multiplexer to clock said converting means in response to said clock signal or to power down said converting means in response to a selected ground.

27. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among predetermined states including a loopback state, an on-hook state, a ringing state, and an off-hook state,

said components include a digital signal processor, and clock controlled CMOS digital intermediate frequency processing (DIF) means, said DIF means having an input connection for receiving baseband digital signals and having an output connection to which it provides corresponding digital signals up converted to an intermediate frequency, and

said limiting means comprises means for producing clock signals of a predetermined frequency, and means for coupling said clock signals to said DIF means to enable DIF means operation only during said loopback function and in time slots in which said subscriber unit is transmitting and is in one of said ringing state and said off-hook state.

28. The subscriber unit in accordance with claim 27 in which said means for coupling clock signals to said DIF means comprises:

means for providing at least one clock signal of predetermined frequency,

receiving means for receiving a binary coded multibit word from said digital signal processing means,

a controllable, signal selecting multiplexer having a plurality of input connections, at least one of which is connected to ground,

means, responsive to at least one bit of said multibit word, for controlling said multiplexer to select either said clock signal or ground, and

means for coupling an output of said multiplexer to clock said DIF means in-response to said clock signal or to power down said DIF means in response to a selected ground.

29. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among at least predetermined state including a loopback state, an on-hook state, a ringing state, and an off-hook state,

said components include a digital signal processor, command signal coupling means, and clock controlled CMOS finite impulse response (FIR) processing means, and CMOS sample rate interpolation (INT) processing means, said FIR processing means having an input connection for receiving complex, baseband, digital signal samples at a first sample rate and having an output connection to which it provides corresponding pulse shaped samples at a second lower sample rate, said INT processing means having an input connection for receiving said complex samples at said second sample rate and having an output connection to which it provides corresponding samples at a third sample rate higher than said first sample rate, and

said limiting means comprises means for producing clock signals of a predetermined frequency, and means for coupling said clock signals to said FIR processing means and INT processing means to enable operation thereof only during said loopback state and in time slots in which said subscriber unit is transmitting in one of said ringing state and said off-hook state.

30. The subscriber unit in accordance with claim 29 in which said means for coupling clock signals to said FIR means and said INT means comprises:

means for providing at least one clock signal of predetermined frequency,

receiving means for receiving a binary coded multibit word from said digital signal processing means,

a controllable, signal selecting multiplexer having a plurality of input connections, at least one of which is connected to ground,

means, responsive to at least one bit of said multibit word, for controlling said multiplexer to select either said clock signal or ground, and

means for coupling an output of said multiplexer to clock said FIR processing means and said INT processing means in response to said clock signal or to power down said FIR processing means and said INT processing means in response to a selected ground.

31. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among at least predetermined state including a loopback state, an on-hook state, a ringing state, and an off-hook state,

said components include a digital signal processor, and a radio frequency, RF, section including a receive portion having an input connection for receiving analog radio frequency signals and having an output connection at which it provides analog intermediate frequency signals, further including a transmit portion having an input connection for receiving analog intermediate frequency signals and having an output connection at which it provides corresponding analog radio frequency signals, and including a timing and control logic portion for providing local oscillator frequency signals to said transmit portion and said receive portion, and

said limiting means comprises means, in said timing and control logic portion, for providing power consumption level control signals to said transmit portion and to said receive portion, means for coupling said power consumption level control signals to said transmit portion to power down at least a segment of said transmit portion in ones of said time slots except time slots in which said subscriber unit is transmitting and is in one of said ringing state, said off-hook state and an intermittent off-hook state,

means for coupling said power consumption level control signals to said receive portion to power down at least a segment of said receive portion in ones of said time slots except time slots in which said subscriber unit is receiving and is in one of said off-hook state and an intermittent off-hook state.

32. The subscriber unit in accordance with claim 31 in which:

said segment of said transmit portion of said RF section comprises a first IF segment, a second IF segment including at least one amplifier, an up converting mixer for raising a signal of said second IF segment to radio frequency and including a local oscillator input including an amplifier, and a radio frequency segment including at least one radio frequency amplifier and one power amplifier, and

said power consumption level control signals are applied to said transmit portion to power down all of said amplifiers.

33. The subscriber unit in accordance with claim 31 in which:

said segment of said receive portion of said RF section comprises an RF segment including at least one amplifier, a first down converting mixer for reducing radio frequency signals to an IF signal and including a local oscillator input including an amplifier, an IF segment including at least one IF amplifier and an automatic gain control amplifier, and a second down converting mixer for reducing said IF signal to a baseband signal and including a local oscillator input including an amplifier, and

said power consumption level control signals are applied to said receive portion to power down all of said amplifiers and said second down converting mixer.

34. The subscriber unit in accordance with claim 9 in which:

said subscriber unit operates among at least predetermined loopback, on-hook, ringing, and off-hook functions, said components include a digital signal processor, and a radio frequency section including a receive portion having an input connection for receiving analog radio frequency signals and having an output connection at which it provides analog intermediate frequency signals, further including a transmit portion having an input connection for receiving analog intermediate frequency signals and having an output connection at which it provides corresponding analog radio frequency signals, and including a timing and control logic portion providing local oscillator frequency signals to said transmit and receive portions,

said receive portion includes a radio frequency segment for receiving and amplifying radio frequency signals, a first down converting mixer for reducing the frequency of amplified radio frequency signals from said radio frequency segment to an intermediate frequency signal, an intermediate frequency segment for amplifying said intermediate frequency signal, a second down converting mixer for reducing the frequency of the amplified intermediate frequency signal to a baseband signal,

a selectable loopback connection is provided for placing said subscriber unit in a loopback state by connecting an output of said transmit portion to an input of said intermediate frequency segment, and

said limiting means comprises means for providing power consumption level control signals to said transmit portion and to said receive portion, one of said control signals being a loopback signal, and

means for coupling said loopback power consumption level control signal to said receive portion both to select said loopback connection and to power up in said receive portion only said intermediate frequency segment, said second down converting mixer, and its local oscillator input amplifier in only said loopback state.

35. The subscriber unit in accordance with claim 9 in which a first group of said plurality of circuit components are connected in a receive signal path through said subscriber unit and a second group of said plurality of circuit components are connected in a transmit signal path through said subscriber unit, said subscriber unit has a standby mode of operation in which it monitors a TDMA system radio control channel to receive a control message directed to said subscriber unit and transmits a response message on said channel, and said limiting means comprises:

means, activated once in each nth one of said TDMA frames, for powering up at least a portion of said group of receive path circuit components in a first time slot of said each nth frame to receive in one of said each nth frames a control message directed to said subscriber unit, n being at least one, and

means, responsive to reception of said control message, for powering up at least a portion of said group transmit path circuit components in a second time slot of one of said each nth frames to enable response to said control message.