High speed programmable counter

• US 5,666,390 A
• Filed: 09/28/1995
• Issued: 09/09/1997
• Est. Priority Date: 09/28/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Morzano, Christopher K.
• Primary Examiner(s): Wambach, Margaret Rose
• Application Number:
  US08/535,655
• Time in Patent Office: 712 Days
• Field of Search: 377/52, 377/51, 377/27, 377/110
• US Class Current: 377/52
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: H03K 23/66 with a variable counting base, e.g. by presetting or by adding or suppressing pulses
• CPC Class Codes: H03K 23/665 by presetting

Abstract

A digital counter allows the provision of start and stop values in order to allow it to be configurable to any length. The counter rolls over to zero at a maximum value and proceeds to count until it reaches an indicated stop count. At that point, it proceeds to the start count and continues counting. The counter counts half bytes of a cell of data for transmission to and from a multiport DRAM in accordance with communication protocols, such as asynchronous transfer mode (ATM.).

Claims

1. A programmable counter comprising:

multiple latches for providing a count output;

a first circuit for providing a start count value coupled to said latches;

a second circuit for providing a stop count value coupled to said latches;

a third circuit coupled to the latches for providing a maximum count value to said latches; and

,

a compare circuit coupled to the second circuit and the latches for comparing the count with the stop count.

2. The programmable counter of claim 1 wherein the third circuit comprises a toggle controller for receiving the count value and selectively providing toggle control signals to inputs of the latches.

3. The programmable counter of claim 2 wherein the toggle controller is provided the count from the latches and further provides a toggle control signal to each latch causing each latch to generate a 0 bit count based on a predetermined rollover value of said count.

4. The programmable counter of claim 3 wherein the rollover value of said count is decimal 111.

5. The programmable counter of claim 2 wherein the latches further comprise circuitry for resetting the value of the count to the start value upon reaching the stop count.

6. The programmable counter of claim 1 wherein the latches further comprise circuitry for resetting the value of the count to the start value upon reaching the stop count.

7. The programmable counter of claim 1 wherein each latch corresponds to one bit of a 7-bit count value.

8. A programmable counter comprising:

multiple latches for providing a count output;

a first circuit for providing a start count value coupled to said latches;

a second circuit for providing a stop count value coupled to said latches;

a compare circuit coupled to the second circuit and the latches for comparing the count with the stop count to provide a match indication causing the latches to be reset.

9. A method of counting implemented by digital logic circuitry comprising the following steps:

limiting the count to a maximum count value;

providing a start count value;

providing a stop count value which may be less than the start count value;

counting sequentially from said start count value;

resetting the count to 0 upon reaching the maximum count value; and

continuing to count from 0 until the stop count value is reached.