Redundant processing system architecture

• US 5,666,483 A
• Filed: 09/22/1995
• Issued: 09/09/1997
• Est. Priority Date: 09/22/1995
• Status: Expired due to Term

• Current Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: McClary, Charles R.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): LE, DIEU MINH T
• Application Number:
  US08/532,949
• Time in Patent Office: 718 Days
• Field of Search: 395/182.08, 395/182.09, 371/36, 364/424.013, 364/424.091, 364/443
• US Class Current: 714/10
• CPC Class Codes: G06F 11/1675 Temporal synchronisation or re-synchronisation of redundant processing components
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components
• CPC Class Codes: G06F 11/188 where exact match is not required

Abstract

Disclosed is a fault-tolerant and/or fail-safe information processing system architecture for handling information from a plurality of independent subsystems which provide information related to selected input quantities, and which includes a plurality of redundant information processors for deriving specific processor output data as a function of the selected subsystem input quantities.

Claims

1. A data processing system architecture comprising:

a selected number of data processor means, where each data processor means

(i) is independent of each other,

(ii) includes an input means for receiving processor input data, and

(iii) is operative for deriving specific processor output data as a function of said processor input data;

a plurality of subsystems, where each subsystem

(i) is independent of each other,

(ii) is operative for determining subsystem information in response to at least one predetermined input quantity, and

(iii) includes a set of subsystem data output means where the number of said subsystem data output means of the set is equal to said selected number of said plurality of data processor means, and where each subsystem data output means of said set of subsystem data output means (a) is independent of each other, and (b) provides subsystem output data related to said subsystem information associated with said set of subsystem data output means, and (c) provides subsystem output data which corresponds to a unique sample time; and

data coupling means for selectively presenting said subsystem output data associated with said set of subsystem data output means of each of said plurality of subsystems to said plurality of data processor means such that (a) each data processor means uniquely receives said subsystem output data from one group of data output means, where said group of data output means consists of only a unique one of said subsystem data output means of the set of subsystem data output means of each one of said plurality of subsystems, and (b) each subsystem data output means of the group provides said subsystem data output to only one of said plurality of data processor means, and in which the subsystem output data of said group of subsystem data output means corresponds to a common sample time.

2. The data processing system architecture of claim 1 where in said data coupling means includes a plurality of data transfer and control means equal in number to said selected number of said plurality of data processor means, where each one of said plurality of said data transfer and control means

(i) is independent of each other,

(ii) is coupled to only one of said plurality of data processor means not coupled to any other data transfer and control means, and said subsystem data output means associated with one group of said subsystem data output means, and

(iii) is operable for permitting the transfer of said subsystem output data associated With said group of subsystem data output means to said processor input means of said data processor means associated with said group of subsystem data output means.

3. The data processing system architecture of claim 1 wherein said data coupling means includes a separate data bus associated with each data processor input means and to only one of said group of subsystem data output means.

4. The data processing system architecture of claim 1 wherein said data coupling means includes a separate data bus associated with each subsystem data output means of each of said plurality of subsystems, and each separate data bus is coupled to said processor input means of only one of said plurality of data processor means and only one of said subsystem data output means.

5. The data processing system architecture of claim 1 wherein each of said data processor means is operative for determing identical output information in response to like-kind subsystem information.

6. The data processing system architecture of claim 5 further comprising processor voter means responsive to said processor output data of each of said plurality of data processor means for detecting any faults in said data processing system architecture.

7. The data processing system architecture of claim 1 wherein said plurality of subsystems includes:

six gyro subsystems, each having an angular rotation sensor associated therewith, and in which each gyro Subsystem is responsive to angular rotation along an axis different than any of the other remaining gyro subsystems; and

six accelerometer subsystems, each having an acceleration sensor associated therewith, and in which each accelerometer subsystem is responsive to acceleration along an axis different than any of the other remaining accelerometer subsystems.

8. The data processing system architecture of claim 7 wherein each of said angular rotation sensors is a ring laser gyro.

9. The data processing system architecture of claim 8 wherein each of said gyro subsystems includes a plurality of gyro subsystem data output means equal in number to said selected number of data processor means, and in which each gyro subsystem data output means includes an accumulator which provides a representation of the change in angular rotation from one sample time to another sample time.

11. The data processing system architecture of claim 1 wherein:

said first data coupling means includes a first data transfer and control means coupled to said first data processor means and said first subsystem data output means of each set associated with each of said plurality of subsystems, and is operable for permitting the transfer of said subsystem output data from those ones of said first subsystem data output means to said first processor input means, and which said subsystem output data associated therewith corresponding to a first common sample time;

said second data coupling means includes a second data transfer and control means coupled to said second data processor means and said second subsystem data output means of each set associated with each of said plurality of subsystems, and is operable for permitting the transfer of said subsystem output data from those ones of said second subsystem data output means to said second processor input means, and which said subsystem output data associated therewith corresponding to a second common sample time; and

said third data coupling means includes a third data transfer and control means coupled to said third data processor means and said third subsystem data output means of each set associated with each of said plurality of subsystems, and is operable for permitting the transfer of said subsystem output data from those ones of said third subsystem data output means to said third processor input means, and which said subsystem output data associated therewith corresponding to a third common sample time.

10. A data processing system architecture comprising:

at least first, second, and third data processor means, where each data processor means

(i) is independent of each other,

(ii) includes an input means for receiving processor input data, and

(iii) is operative for deriving specific processor output data as a function of said processor input data;

a plurality of subsystems, where each subsystem

(i) is independent of each other,

(ii) is operative for determining subsystem information in response to at least one predetermined input quantity, and

(iii) includes a set of first, second, and third subsystem data output means, and where each subsystem data output means of said set (a) is independent of each other, (b) provides subsystem output data related to said subsystem information associated with said set of said subsystem of subsystem data output means, and (c) provides subsystem output data which corresponds to a unique sample time; and

a first data coupling means for coupling said first subsystem data output means associated with each of said plurality of subsystems to said input means of said first data processor means thereby providing said subsystem output data associated with said first subsystem data output means associated with each of said plurality of subsystems as processor input data for said first data processor means;

a second data coupling means for coupling said second subsystem data output means associated with each of said plurality of subsystems to said input means of said second data processor means thereby providing said subsystem output data associated with said second subsystem data output means associated with each of said plurality of subsystems as processor input data for said second data processor means;

a third data coupling means for coupling said third subsystem data output means associated with each of said plurality of subsystems to said input means of said third data processor means thereby providing said subsystem output data associated with said third subsystem data output means associated with each of said plurality of subsystems as processor input data for said third data processor means.

12. A data processing system architecture for a skewed axis redundant inertial reference system comprising:

a selected number of redundant data processor means, where each redundant data processor means

(i) is independent of each other,

(ii) includes an input means for receiving like-kind processor input data, and

(iii) is operative for deriving inertial reference output data as a function of said like-kind processor input data;

at least six gyro subsystems, each having an angular rotation sensor associated therewith, and in which each gyro subsystem is responsive to angular rotation along a selected sensing axis which is skewed relative to the sensing axis of any of the other remaining gyro subsystems, and where each of said at least six gyro subsystems are

(i) independent of each other, and

(ii) includes a set of gyro subsystem data output means where the number of said gyro subsystem data output means of the set is equal to said selected number of said plurality of data processor means, and where each gyro subsystem data output means of said set of gyro subsystem data output means (a) is independent of each other, and (b) provides gyro subsystem output data corresponding to the sensed angular rotation about the sensing axis associated therewith, and (c) provides said gyro subsystem output data which corresponds to a unique sample time;

at least six accelerometer subsystems, each having an angular rotation sensor associated therewith, and in which each accelerometer subsystem is responsive to angular rotation along a selected sensing axis which is skewed relative to the sensing axis of any of the other remaining accelerometer subsystems, and where each of said at least six accelerometer subsystems are

(i) independent of each other, and

(ii) includes a set of accelerometer subsystem data output means where the number of said accelerometer subsystem data output means of the set is equal to said selected number of said plurality of data processor means, and where each accelerometer subsystem data output means of said set of accelerometer subsystem data output means (a) is independent of each other, and (b) provides accelerometer subsystem output data corresponding to the sensed angular rotation about the sensing axis associated therewith, and (c) provides said accelerometer subsystem output data which corresponds to a unique sample time; and

data coupling means for selectively presenting (i) said gyro subsystem output data associated with said set of gyro subsystem data output means of each of said plurality of said at least six gyro subsystems to said plurality of data processor means, and (ii) said accelerometer subsystem output data associated with said set of accelerometer subsystem data output means of each of said plurality of said at least six accelerometer subsystems to said plurality of data processor means, such that (a) each data processor means uniquely receives said gyro subsystem output data and said accelerometer subsystem output data from one group of data output means, where said group of data output means consists of (i) only a unique one of said gyro subsystem data output means of the set of gyro subsystem data output means of each one of said plurality of gyro subsystems, and (ii) only a unique one of said accelerometer subsystems data output means of the set of accelerometer subsystem data output means of each one of said at least six accelerometer subsystems, and (c) each gyro subsystem data output means and accelerometer subsystem data output means of the group of data output means is presented as processor input data to only one of said plurality of data processor means, and in which the gyro subsystem output data of said group of said gyro subsystems data output means and the accelerometer subsystem output data of said group of accelerometer subsystem output data means corresponds to a common sample time.

13. The data processing system architecture of claim 12 further comprising processor voter means responsive to said inertial reference output data from each of said plurality of data processor means for detecting any faults in said data processing system architecture.