Information processing system having multiple modules and a memory on a bus, where any module can lock an addressable portion of the memory by sending retry signals to other modules that try to read at the locked address

• US 5,666,515 A
• Filed: 12/04/1996
• Issued: 09/09/1997
• Est. Priority Date: 02/18/1993
• Status: Expired due to Fees

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: Nguyen, Kha, White, Theodore Curt, Sheth, Jayesh Vrajlal, Tran, Dan Trong
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): BRAGDON, REGINALD GLENWOOD
• Application Number:
  US08/759,996
• Time in Patent Office: 279 Days
• Field of Search: 395/479, 395/482, 395/477, 395/726
• US Class Current: 711/152
• CPC Class Codes: G06F 12/1425 the protection being physical, e.g. cell, word, block

Abstract

Apparatus and method are provided for preventing access to a memory location while that memory location is being modified, updated, etc. When a peripheral device wishes to accomplish such a change at a memory location, it provides the changed data and its intended memory address to an input/output unit. The input/output unit includes a plurality of separately controlled multiplexers, the number of multiplexers being preferably selected to correspond to the size (in bits) of a memory data word or packet divided by the size (in bits) of a peripheral data word. The input/output unit reads the data at the requested memory location into an input buffer, combines the portions of that data not to be modified with the data provided by the peripheral, and sends the result back to the same memory location. During this Read-Modify-Write operation, the input/output unit also monitors the system bus for any attempts or requests to read data from, or write data to, the memory address for which the Read-Modify-Write operation is being performed. In such event, a signal is sent to the module making such attempt or request, asking or telling that module to wait. That signal is removed when that Read-Modify-Write operation is completed.

Claims

1. An information processing system, comprising:

a memory having a plurality of individually addressable memory locations;

a bus connected to said memory;

at least one first module connected to said bus and capable of reading information from or writing information to said memory via said bus; and

a second module connected to said bus;

wherein said second module includes a circuit which executes a read-modify-write command by;

a) sending a first read command with a particular address to said memory, b) subsequently and independently of any command from said first module, sending a first write command with said particular address to said memory, and c) sending a control signal to said first module, in response to said first module sending a second read command with said particular address to said memory between said commands from said second module, which directs said first module to retry only said second read command and permits said first module to send additional read commands, before said first write command, with any address that differs from said particular address;

wherein said first module includes a circuit which retries said second read command solely in response to just said control signal;

and wherein said memory includes a circuit which executes said first read command and said first write command from said second module without ever signaling said first module that said first module has accessed an address which is involved in said read-modify-write command.